參數(shù)資料
型號： TP3410J
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 數(shù)字傳輸電路
英文描述： TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver
中文描述： DATACOM, DIGITAL SLIC, CDIP28
封裝： CERAMIC, DIP-28
文件頁數(shù)： 6/32頁
文件大?。?/td> 436K
代理商： TP3410J
Functional Description
(Continued)
Framing
12x(2B
a
D)
Overhead Bits (M
1
–M
6
)
Quat Positions
1–9
10–117
118s
118m
119s
119m
120s
120m
Bit Positions
1–18
19–234
235
236
237
238
239
240
Superframe
Y
Basic Frame
Y
Sync Word
2B
a
D
M
1
M
2
M
3
M
4
M
5
M
6
1
1
ISW
2B
a
D
eoca
1
eoca
2
eoca
3
act
1
1
2
SW
2B
a
D
eocd
m
eoci
1
eoci
2
dea
1
febe
3
SW
2B
a
D
eoci
3
eoci
4
eoci
5
1
crc
1
crc
2
4
SW
2B
a
D
eoci
6
eoci
7
eoci
8
1
crc
3
crc
4
5
SW
2B
a
D
eoca
1
eoca
2
eoca
3
1
crc
5
crc
6
6
SW
2B
a
D
eocd
m
eoci
1
eoci
2
1
crc
7
crc
8
7
SW
2B
a
D
eoci
3
eoci
4
eoci
5
uoa
crc
9
crc
10
8
SW
2B
a
D
eoci
6
eoci
7
eoci
8
aib
crc
11
crc
12
2, 3, . . .
1
ISW
(a) Network
x
NT
Framing
12x(2B
a
D)
Overhead Bits (M
1
–M
6
)
Quat Positions
1–9
10–117
118s
118m
119s
119m
120s
120m
Bit Positions
1–18
19–234
235
236
237
238
239
240
Superframe
Y
Basic Frame
Y
Sync Word
2B
a
D
M
1
M
2
M
3
M
4
M
5
M
6
1
1
ISW
2B
a
D
eoca
1
eoca
2
eoca
3
act
1
1
2
SW
2B
a
D
eoc
dm
eoci
1
eoci
2
ps
1
1
febe
3
SW
2B
a
D
eoci
3
eoci
4
eoci
5
ps
2
crc
1
crc
2
4
SW
2B
a
D
eoci
6
eoci
7
eoci
8
ntm
crc
3
crc
4
5
SW
2B
a
D
eoca
1
eoca
2
eoca
3
cso
crc
5
crc
6
6
SW
2B
a
D
eoc
dm
eoci
1
eoci
2
1
crc
7
crc
8
7
SW
2B
a
D
eoci
3
eoci
4
eoci
5
1
crc
9
crc
10
8
SW
2B
a
D
eoci
6
eoci
7
eoci
8
1
crc
11
crc
12
2, 3, . . .
1
ISW
(b) NT
x
Network
Note:
8
c
1.5 ms Basic Frames
e
12 ms/Superframe. NT-to-Network superframe is offset from Network-to-NT superframe by 60
g
2 quats (about 0.75 ms). All
bits other than the Sync Word are scrambled.
Symbols & Abbreviations
e
start-up bit (
e
1 during start-up)
aib
e
alarm indication bit (
e
0 to indicate interrup-
tion)
e
cyclic redundacy check: covers 2B
a
D
a
M
4
1
e
most significant bit
2
e
next significant bit etc.
cso
e
cold-start-only bit (
e
1 to indicate cold-start-
only)
e
turn off bit (
e
0 to announce turn off)
eoc
e
embedded operations channel
a
e
address bits
dm
e
data/message
1
e
message)
i
e
information (data or message)
febe
e
far end block error bit (
e
0 for errored super-
frame)
act
crc
dea
indicator
(0
e
data,
ntm
ps1, ps2
e
power status bits (
e
0 to indicate power prob-
lems)
e
pair of bits forming quaternary symbol
s
e
sign bit (first in quat)
m
e
magnitude bit (second in quat)
sai
e
S-activation-indication bit (
e
1 for S/T activity)
uoa
e
U-only-activation bit (
e
1 to activate S/T)
‘‘1’’
e
reserved bit for future standard (
e
1)
‘‘1
*
’’
e
network indicator bit (
e
1, reserved for network
use)
2B
a
D
e
user data, bits 19–234 in frame
M
e
M-channel, bits 235–240 in frame
SW/ISW
e
synchronization word/inverted synchronization
word, bits 1–18 in frame
e
NT in test mode bit (
e
0 to indicate test mode)
Quat
TABLE I. 2B1Q Superframe Format and Overhead Bit Assignments
6
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