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參數(shù)資料
| 型號： | TP3410J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver |
| 中文描述： | DATACOM, DIGITAL SLIC, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數(shù)： | 12/32頁 |
| 文件大小： | 436K |
| 代理商： | TP3410J |
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Functional Description
(Continued)
TL/H/9151–12
FIGURE 5-1. Format 1
TL/H/9151–13
FIGURE 5-2. Format 2
TL/H/9151–14
FIGURE 5-3. Format 3
Shown with example of Time-slot Assignment, and FS
a
e
FS
b
FIGURE 5. D-Port Interface Timing Using BCLK
7.0 MICROWIRE CONTROL PORT (MW
e
1)
When Format 1, 2, 3 or 4 is used, control information and
maintenance channel data is written into and read back
from the TP3410 via the Microwire port consisting of the
control clock CCLK; the serial data input, CI, and output,
CO; the Chip Select input, CS and the interrupt output INT.
The MW pin must be tied high to enable this port, and the
port may be used regardless of whether the device is pow-
ered up or down.Figures 6 and14 show the timing, which is
compatible with the Microwire port on the HPC and COPs
families of microcontrollers, and Tables II and III list the con-
trol functions and status indicators.
All read and write operations require 2 contiguous bytes. As
shown in Tables II and III, the first byte is the register ad-
dress and the second byte is the data byte. Status Registers
request service under control of the Interrupt Stack, with the
priority order listed in Table III.
To shift data to and from the TP3410, CCLK must be pulsed
high 16 times while CS is low. Data on the CI input is shifted
into the serial input register on the rising edge of each CCLK
pulse; simultaneously, data is shifted out from CO on each
falling edge of CCLK. Bit 7 of byte 1 is shifted first. CS must
return high at the end of the 2nd byte, after which the con-
tents of the input shift register are decoded, and the data is
loaded into the appropriate programmable register. Pulling
CS low also clears the INT pin if it was pulled low; if another
interrupt condition is queued on the Interrupt Stack it can
only pull the INT pin low when CS is high. When CS is high
the CO pin is in the high-impedance state, enabling the CO
pins of many devices to be multiplexed together.
12
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| TP3410J304-X | 功能描述:IC TXRX ISDN BASIC ACC 28-CERDIP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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