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參數(shù)資料
| 型號： | TP3410J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver |
| 中文描述： | DATACOM, DIGITAL SLIC, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 436K |
| 代理商： | TP3410J |
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Functional Description
(Continued)
9.0 COMMAND REGISTER FUNCTIONS
All addressing and bit-level functions are the same for both
the Microwire and GCI Monitor Channels, except where not-
ed. Register addresses are listed in Table II. An asterisk
*
indicates the Power-on Reset state of each function. The
device modes and Transmit M bits should be programmed
while the device is powered down.
9.1 Writing to Command Registers
A command may be written to a register to modify its con-
tents by setting byte 1 bit 0
e
0. Registers CR1, 2, 3, OPR
and the Time-Slot Assignment registers may also be read-
back to verify the contents by addressing each register with
byte 1 bit 0
e
1. In Microwire Mode, if the device has no data
waiting to be read during a command cycle it will return
X
ê
0000 (No Change).
9.2 Reading Back Command Registers for Verification
To read back the current state of one of the write-able regis-
ters, the appropriate readback command must first be load-
ed in via the control channel; this will cause an interrupt to
be sent to the interrupt stack. In Microwire mode the inter-
rupt must be serviced by a read cycle, in which the com-
mand should be a NOP (or a new command). In this cycle
the previously addressed register is read back, with byte 1
bit 0
e
1. In GCI mode, the interrupt stack generates an au-
tonomous one-way message in the Monitor Channel. If any
other interrupt conditions should occur during the readback
command cycle, the readback result will be queued at the
bottom of the stack, and will not generate its interrupt or
message until all other interrupts are cleared.
9.3 Configuration Register CR1: Digital Interface
Byte 2
7
6
5
4
3
2
1
0
FF1
FF0
CK2
CK1
CK0
DDM
CMS
BEX
*
CR1 is set to X
ê
00 at Power-On Reset.
FF1, FF0: Digital System Interface Frame Format
Selection
These bits are effective in Microwire Mode only (MW
e
1).
They select the Digital Interface format as described in Sec-
tion 6.
Format
FF1
FF0
*
1
2
3
4
0
0
1
1
0
1
0
1
CK0–CK2: Digital Interface Clock Select
In Microwire Mode only, and if DSI Master is selected (CMS
e
1), CK0–CK2 bits select from a choice of 5 frequencies
for the BCLK output. (In GCI Mode, these bits have no ef-
fect.) The frequency of 256 kHz is not valid with Format 4.
CK2
CK1
CK0
BCLK Frequency:
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
*
256 kHz Master
512 kHz Master
1536 kHz Master
2048 kHz Master
2560 kHz Master
DDM: Delayed Data Mode Select
For Microwire mode, see Section 6.1: FS Relationship to
Data. In GCI Mode or Format 4 this bit has no effect.
*
DDM
e
0 for non-delayed data mode (see Figure 11 ).
DDM
e
1 for delayed data mode (see Figure 12 ).
CMS: DSI Clock Master/Slave Select
In Microwire Mode (MW
e
1):
CMS
e
0 for DSI Slave; may be used in either LT or NT
Modes
CMS
e
1 for DSI Master; may be used in either LT or NT
Modes, but when in LT Mode, must also send X
ê
1840. See
the TP3410 User’s Manual AN-913 Section 4.5 for details.
In GCI Mode (MW
e
0) this bit has no effect; the MO pin
selects GCI Master or Slave.
BEX: B Channel Exchange
This command enables the two B channels to be ex-
changed as the data passes through the device between
the Digital Interface and the Line in both directions. It should
not be used if any loopback is selected in the device.
*
BEX
e
0 for B channels mapped direct, B1 to B1 and B2
to B2.
BEX
e
1 for B channels exchanged, B1 to B2 and B2 to B1.
9.4 Configuration Register CR2: Device Modes
Byte 2
7
6
5
4
3
2
1
0
SSS
NTS
DMO
DEN
DD
BP1
BP2
0
*
CR2 is set to X
ê
00 at Power-On Reset.
SSS: Superframe Synchronization Select
This bit is effective in LT mode only; in NT mode the SFS pin
is an output. When SSS
e
0, SFS is an input which syn-
chronizes the transmit superframe counter on the line.
When SSS
e
1, SFS is an output superframe marker pulse.
NTS: NT or LT Select
*
NTS
e
0 for LT Mode.
NTS
e
1 for NT Mode.
DEN: D Channel Port Select
*
When DEN
e
0, the D channel port is disabled and the D
bits are transferred on the Br and Bx pins, clocked by BCLK.
The Dx pin must also be tied to GND for correct operation.
When DEN
e
1, the D channel port is enabled; D bits are
transferred on the Dr and Dx pins in a mode selected by the
DMO bit, see Section 6.3.
DMO: D Channel Transfer Mode Select
This bit is significant only when the D channel port is select-
ed (DEN bit
e
1).
When DMO
e
1, D channel data is shifted in and out on Dx
and Dr pins in a continuous mode at 16 kbit/s on the falling
and rising edges of DCLK respectively, see Figure 4.
When DMO
e
0, D channel data is shifted in and out on Dx
and Dr pins in a burst mode at the BCLK frequency when
the assigned time-slots are active, see Figure 5.
DD: 2B
a
D Data Disabling
*
When DD
e
0, 2B
a
D channel transfer is enabled as soon
as the line is completely synchronized.
When DD
e
1, B and D channel transfer is inhibited. The
data transmitted to line is preset to send scrambled 1’s with
the device in NT mode or scrambled 0’s if the device is in LT
17
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