參數(shù)資料
型號: TP3410J
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 數(shù)字傳輸電路
英文描述: TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver
中文描述: DATACOM, DIGITAL SLIC, CDIP28
封裝: CERAMIC, DIP-28
文件頁數(shù): 2/32頁
文件大?。?/td> 436K
代理商: TP3410J
Connection Diagrams
Pin Names for MICROWIRE Mode
TL/H/9151–2
Top View
Pin Names for GCI Mode
TL/H/9151–3
Top View
Order Number TP3410J
See NS Package Number J28A
Pin Descriptions
Pin
Symbol
No.
24
GNDA
9
GNDD1
23
GNDD2
Description
Negative power supply pins, which must
be connected together close to the de-
vice. All digital signals are referenced to
these pins, which are normally at the sys-
tem 0V (Ground) potential.
5
V
CC
A
Positive power supply input for the analog
sections, which must be
a
5V
g
5% and
must be directly connected to V
CC
D.
Positive power supply input for the digital
section, which must be
a
5V
g
5% and
must be directly connected to V
CC
A.
The 15.36 MHz Master Clock input, which
requires either a parallel resonance crystal
to be tied between this pin and XTAL2, or
a CMOS logic level clock input from a sta-
ble source (a TTL Logic ‘‘1’’ level is not
suitable). This clock does not need to be
synchronized to the system clock (BCLK
and FS), see Section 5.1.
8
V
CC
D
21
MCLK/
XTAL
20
XTAL2
The output of the crystal oscillator, which
should be connected to one end of the
crystal, if used; otherwise this pin must be
left open-circuit. Not recommended to
drive additional logic.
10
TSr/
SCLK
This pin has 2 functions: in LT mode it is
an open-drain n-channel TSr output, which
goes low only during the time-slots as-
signed to the B1 and B2 channels at the
Br pin in order to enable the TRI-STATE
control of the backplane line-driver. In NT
mode it is a full CMOS 15.36 MHz syn-
chronous clock output which is frequency-
locked to the received line signal (unlike
the XTAL pins it is not free-running).
Pin
No.
Symbol
Description
22 TSFS
The Transmit Superframe Sync pin, which
indicates the start of each 12 ms transmit
superframe at the U Interface. In NT mode
this pin is always an output. In LT mode it
may be selected to be either an input or
CMOS output via Register CR2; when se-
lected as an output the signal is a square-
wave. Must be tied low if selected as input
yet not driven.
25 LSD/RSFS This pin is an open-drain n-channel Line
Signal Detector output, which is normally
high-impedance and pulls low only when
the device is powered down and an incom-
ing wake-up signal is detected from the
far-end. As an option this pin can be pro-
grammed to be an output indicating the
start of the received superframe at the U
interface; an external pull-up resistor is re-
quired.
The RSFS signal indicates the start of
each 12 ms receive superframe from the U
Interface and is available in NT and LT
modes. The Received Superframe Synch
clock output is accessible on pin 25 by
writing X’1C04 and X’100C (or X’100E)
during device initialization. See TP3410
users manual AN-913, Part II Section
4.18).
Lo
a
Transmit 2B1Q signal differential outputs
4
Lo
b
to the line transformer. When used with an
appropriate 1:1.5 step-up transformer and
the line coupling circuit recommended in
the Applications section, the line signal
conforms to the output specifications in
the ANSI standard.
1
2
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