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參數(shù)資料
| 型號(hào)： | TP3410J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver |
| 中文描述： | DATACOM, DIGITAL SLIC, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大小： | 436K |
| 代理商： | TP3410J |
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Functional Description
(Continued)
6.1 FS Relationship To Data (Microwire Mode)
For applications on a line-card, in DSI Slave Mode, the B
and D channel slots can be interfaced to a Time-Division
Multiplexed (TDM) bus and assigned to a time-slot. The rep-
etition rate of the FS input signals must be 8 kHz and must
be synchronized to the BCLK input, which may be any fre-
quency from 256 kHz to 4.096 MHz in 8 kHz increments.
Two different relationships may be established between the
FS inputs and the actual time-slots on the PCM busses by
setting the DDM bit in Control Register CR1, see Figures 3,
11 and 12. Non-delayed data mode is similar to long frame
timing on the TP3050/60 series of devices (COMBO I): the
time-slots are defined by the 8-bit duration FSa and FSb
signals. The alternative is to use Delayed Data Mode, which
is similar to short frame sync timing on COMBO I, in which
each FS input indicates the start of the first time-slot.
Serial B channel data is shifted into the Bx input during each
assigned Transmit time-slot on the falling edges of BCLK.
During each assigned Receive time-slot, the Br output shifts
data out on the rising edges of BCLK. Also, with the device
in LT Mode, the TSr pin is an open drain n-channel pull-
down output which goes low during the selected time-slots
for the received B1 and B2 channels at the Br pin to control
the TRI-STATE Enable of a backplane line-driver; it is high-
impedance at all other times.
In NT Mode, when DSI Master mode is selected, FSa and
FSb are outputs indicating the B1 (or TS0) and the B2 (or
TS1) channels respectively. BCLK is also an output at the
serial data shift rate, which is dependent on the format se-
lected. Again, either a delayed or non-delayed relationship
between FSa, FSb and the start of the first time-slot can be
selected.
6.2 B Channel Time-slot Assignment; Format 3 Only
(Microwire Mode)
In Format 3 only, the TP3410 provides programmable time-
slot assignment for selecting the Transmit and Receive B
channel time-slots. Following power-on, the device is auto-
matically in Non-delayed Data Mode; if Delayed Data Mode
is required it must first be selected (see CR1) prior to using
Time-slot Assignment, and the FS pulses must conform to
the Delayed Data timing format. The actual transmit and
receive time-slots are then determined by the internal Time-
slot Assignment counters, programmed via Control Regis-
ters TXB1, TXB2, RXB1 and RXB2. Normally used in DSI
Slave mode, Format 3 allows a frame to consist of up to 64
time-slots of 8 bits each with BCLK up to 4.096 MHz.
A new assignment becomes active on the second frame
following the end of the 16-bit Chip Select.
6.3 D Channel Port Selection (Microwire Mode)
In any of the DSI Formats, the 2 D channel bits per frame
may either be multiplexed with the B channels on the Bx
and Br pins, or may be accessed via the separate D channel
port consisting of Dx and Dr. Furthermore, when using the
separate D port the data shift clock may either be a continu-
ous, unframed data stream using the 16 kHz clock output at
DCLK, see Figure 4, or may use the BCLK, see Figure 5.
Selection of these options is via Control Register CR2.
6.4 D Channel Time-Slot Assignment
In addition to B channel TSA, Format 3 allows independent
Time Slot Assignment for the Transmit and Receive D chan-
nels, which may be programmed via Registers TXD and
RXD. As with the B channels, up to 64 time-slots are avail-
able if BCLK
e
4.096 MHz, and in addition the 2 D bits may
be assigned, in pairs, to specific bit locations within the
time-slot; that is in bits 1 and 2; 3 and 4; 5 and 6; or 7 and 8.
D channel TSA may be used either with the D channel multi-
plexed with the B channel data, or with the separate D
Channel port clocked with BCLK; it cannot be used with the
16 kHz clock option at DCLK.
Summary of DSI Slave Mode Options
Function
Format Number
1
2
3
4
FSa
FSb
Non-Delayed Timing
Delayed Timing
Tx and Rx Frames with
Any Phase
TSA Available
D Port Available
Tx B1
Rx B1
Yes
Yes
Yes
Tx B1
Rx B1
No
Yes
Yes
Tx TS0
Rx TS0
Yes
Yes
Yes
Tx B1
Rx B1
Yes
No
Yes
No
Yes
No
Yes
Yes
Yes
No
Yes
Summary of DSI Master Mode Options
Function
Format Number
1
2
3
4
FSa
FSb
FS Formats
B1
B2
Non-
Delayed
and
Delayed
No
Yes
B1
B2
TS0
TS1
Non-
Delayed
and
Delayed
Yes
Yes
B1
B2
Non-
Delayed
Only
Delayed
Only
TSA Available
D Port Available
No
Yes
No
Yes
Note:
All Formats: Tx and Rx frames always aligned.
TL/H/9151–11
FIGURE 4. D-Port Interface Timing Using DCLK in 16 kHz Mode
11
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3410J304 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-ISDN TRANSCEIVER |
| TP3410J-304 | 制造商:Texas Instruments 功能描述:ISDN LINE INTERFACE, BASIC, 28 Pin, Ceramic, DIP |
| TP3410J304/NOPB | 功能描述:IC TRANSCEIVER MONOLITHIC 28CDIP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| TP3410J304-X | 功能描述:IC TXRX ISDN BASIC ACC 28-CERDIP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| TP3410N304 | 制造商:OC White Company 功能描述:ISDN U HDLC Interface 1-Line 160Kbps 5V 28-Pin CDIP |
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