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參數(shù)資料
| 型號： | TP3410J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver |
| 中文描述： | DATACOM, DIGITAL SLIC, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 436K |
| 代理商： | TP3410J |
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Functional Description
(Continued)
RFS: Remote Febe Select
*
RFS
e
1 (default state)
The state of the outgoing bit is computed based on the state
of the TFB (bit 1) in TXM56 register. The TFB blt is set
e
0
by the software to allow a febe blt from an adjacent DSL to
be forwarded to the next section in the next superframe.
This bit is self resetting (to 1) in Rev. 3.x devices. This is a
change from the Rev. 2.x devices. If RFS
e
0, then the
outgoing febe does not depend on the state of the TFB blt
in TXM56 register.
LFS: Local Febe Select
*
LFS
e
1 (default state)
The state of the outgoing febe bit is computed using the
incoming nebe blt. If LFS
e
0, the outgoing febe is not
dependent on the incoming nebe.
Example of use:
A flexible control of the outgoing febe bit is provided to sup-
port the Segmented and Path Performance Monitoring rec-
ommendations in Bellcore TR 397.
For Rev. 2.8 type operation, set RFS
e
1, LFS
e
1 and
TFB0
e
1. This setting will cause the transmit febe to be
computed as OR of the incoming nebe blt and the state of
the TFB bit in TXM56 (representing the adjacent section
febe to be forwarded).
9.7 Configuration Registers TXB1, TXB2, RXB1,
RXB2: B Channel TSA
These registers are effective only when Format 3 is select-
ed.
TXB1 assigns the Transmit time slot for the B1 channel.
TXB2 assigns the Transmit time slot for the B2 channel.
RXB1 assigns the Receive time slot for the B1 channel.
RXB2 assigns the Receive time slot for the B2 channel.
Register TXB1
Byte 2
7
6
5
4
3
2
1
0
0
0
TS5
TS4
TS3
TS2
TS1
TS0
At Power-On Reset this register is initialized to X
ê
00.
Register TXB2
Byte 2
7
6
5
4
3
2
1
0
0
0
TS5
TS4
TS3
TS2
TS1
TS0
At Power-On Reset this register is initialized to X
ê
01.
Register RXB1
Byte 2
7
6
5
4
3
2
1
0
EB1
ED
TS5
TS4
TS3
TS2
TS1
TS0
At Power-On Reset this register is initialized to X
ê
00.
Register RXB2
Byte 2
7
6
5
4
3
2
1
0
EB2
0
TS5
TS4
TS3
TS2
TS1
TS0
*
At Power-On Reset this register is initialized to X
ê
01.
B Channels Time-Slot Assignment: TS5–TS0
The TS5–TS0 bits define the binary number of the time-slot
when the B channel selected is shifted to or from the Bx and
Br pins; time-slots are numbered from 0 to 63. New time-slot
assignments become effective only at the beginning of a
frame.
B1 and D Channel Enables: EB1; ED
*
EB1
e
0 to disable the B1 channel; B1 is high-impedance
at Br.
EB1
e
1 to enable the B1 channel (must also set DD
e
0 in
CR2).
*
ED
e
0 to disable the D channel; D is high-impedance at
Br or Dr.
ED
e
1 to enable the D channel (must also set DD
e
0 in
CR2).
B2 Channel Enable: EB2
EB2
e
0 to disable the B2 channel; B2 is high-impedance
at Br.
EB2
e
1 to enable the B2 channel (must also set DD
e
0 in
CR2).
9.8 Configuration Register TXD:
Transmit D Channel TSA
This register is effective only when Format 3 is selected. D
channel TSA may be used when the D channel is accessed
either via the Bx/Br or Dx/Dr pins, but the D channel port
must be clocked with BCLK (DMO
e
0 in CR2).
Byte 2
7
6
5
4
3
2
1
0
DX5
DX4
DX3
DX2
DX1
DX0
SX1
SX0
*
At Power-On Reset this register is initialized to X
ê
08.
Transmit D Channel Time-Slot Assignment Select:
DX5–DX0, SX1–SX0
DX5–DX0 bits define the binary number of the 8-bit wide
time-slot, where time-slots are numbered from 0 to 63. With-
in this selected time-slot, the SX1 and SX0 bits define the 2-
bit wide sub-slot for the 2 D channel bits. Sub-slots are num-
bered 0 to 3, as shown in Figures 5, 11 and 12 and the
following table. New time-slot and sub-slot assignments be-
come effective only at the beginning of a frame.
Sub-Slot
Bit Positions
within Time-Slot
SX1
SX0
*
0
0
1
1
0
1
0
1
1, 2
3, 4
5, 6
7, 8
9.9 Configuration Register RXD:
Receive D Channel TSA
This register is effective only when Format 3 is selected. D
channel TSA may be used when the D channel is accessed
either via the Bx/Br or Dx/Dr pins, but the D channel port
must be selected in the burst mode (DMO
e
0 in CR2).
19
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