- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385009 > TP3410J (NATIONAL SEMICONDUCTOR CORP) TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver PDF資料下載
參數(shù)資料
| 型號(hào)： | TP3410J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver |
| 中文描述： | DATACOM, DIGITAL SLIC, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數(shù)： | 20/32頁 |
| 文件大?。?/td> | 436K |
| 代理商： | TP3410J |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
Functional Description
(Continued)
Byte 2
7
6
5
4
3
2
1
0
DR5
DR4
DR3
DR2
DR1
DR0
SR1
SR0
*
At Power-On Reset this register is initialized to X
ê
08.
Receive D Channel Time-Slot Assignment Select:
DR5–DR0, SR1–SR0
DR5–DR0 bits define the binary number of the 8-bit wide
time-slot, where the time-slots are numbered from 0 to 63.
Within this selected time-slot, the SR1 and SR0 bits define
the binary number of the 2 D channel bits. Sub-slots are
numbered 0 to 3, as shown in Figure 12 and the following
table. New time-slot and sub-slot assignments become ef-
fective only at the beginning of a frame.
Sub-Slot
Bit Positions
within Time-Slot
SR1
SR0
*
0
0
1
1
0
1
0
1
1, 2
3, 4
5, 6
7, 8
9.10 Configuration Register OPR:
Overhead Bit Processing
This register controls the enabling/disabling of conditions
which are sent to the Interrupt Stack (see 10.1) as a result
of new data in the RXM4 and RXM56 Overhead Bits Regis-
ters, and the number of consecutive times a new bit or mes-
sage is received before being validated. Flexibility is there-
fore provided to use hardware, external firmware routines or
a combination of both for validation.
Byte 2
7
6
5
4
3
2
1
0
CIE
EIE
FIE
OB1
OB0
OC1
OC0
0
*
At Power-On Reset this register is initialized to X
ê
00.
Near-End CRC Interrupt Enable: CIE
CIE
*
0
No Interrupt if near-end crc error (Block Error
Counters still count).
1
RXM56 Status Register Interrupt is generated, with
NEB
e
0, each superframe in which the locally-
generated crc result does not match the crc in the
received superframe.
Block Error Counter Interrupt Enable: EIE
EIE
*
0
No Interrupt or Monitor channel message from
Block Error Counters.
1
Block Error Counter Interrupts enabled.
febe Bit Interrupt Enable: FIE
FIE
*
0
1
No Interrupt if febe
e
0 received (BEC1 still counts).
RXM56 Status Register Interrupt is generated, with
RFB
e
0, each superframe in which febe
e
0 is
received.
Receive Overhead Bits Interrupt Enable: 0B1, 0B0
These bits determine how many consecutive superframes
must be received with the same new data in any of the
overhead bit positions M41–M48, M51, M52 and/or M61
before an Interrupt(s) is generated for the RXM4 and/or
RXM56 Register, as appropriate. Note that validation check-
ing of the ‘‘a(chǎn)ct’’ and ‘‘dea’’ bits during activation/deactiva-
tion is not affected by OB1/OB0.
OB1
*
0
OB0
0
Interrupt every superframe (no checking).
0
1
Interrupt if any bit changed from previous
superframe.
1
0
2 consecutive times for same new bit(s)
before Interrupt.
1
1
3 consecutive times for same new bit(s)
before Interrupt.
Receive Embedded Operations Channel Interrupt
Enable: OC1, OC0
These bits determine how many consecutive half-super-
frames must be received with the same new address or data
in the Embedded Operations Channel before an Interrupt is
generated for the RX EOC Register.
OC1
*
0
OC0
0
Interrupt every received eoc message (no
checking).
0
1
Interrupt every received eoc message
which differs from previous message.
1
0
2 consecutive times for same new message
before Interrupt.
1
1
3 consecutive times for same new message
before Interrupt.
9.11 Transmit M4 Channel Register TXM4
(Write Only)
When the line is superframe synchronized, the device trans-
mits the contents of this register to the line in the M4 over-
head bit field once per superframe.
Byte 2
7
6
5
4
3
2
1
0
ACT
M42
M43
M44
M45
M46
M47
M48
At Power-On Reset, and each time the device is Deactivat-
ed (or an Activation attempt fails), this register is initialized
to X
ê
7F.
ACT Bit
The ACT bit in the TXM4 register does not normally control
the ‘‘a(chǎn)ct’’ bit in the M4 word transmitted to the line (see
Table I). That ‘‘a(chǎn)ct ’’ bit is generated automatically within the
device and can be controlled through the Activation Control
Register (see Table I and Section 11.0, Activation/Deactiva-
tion). In normal operation the ACT bit in the TXM4 register is
ignored.
M42–M48 Bits
As shown in the Frame Formats in Table I, the functions of
these bits depend on the mode of the device. They should
be programmed as appropriate prior to an Activation Re-
quest, with the exception of the M42 bit in LT Mode. This is
the dea bit, which is automatically controlled by the device
in response to AR and DR commands; the M42 bit in this
register is normally ignored in LT mode.
20
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TP3420AJ | ISDN S/T Interface Device |
| TP3420A | ISDN S/T Interface Device |
| TP3420AN | ISDN S/T Interface Device |
| TP3420AV | ISDN S/T Interface Device |
| TP3464 | MICROWIRE⑩ Interface Device (MID) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3410J304 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-ISDN TRANSCEIVER |
| TP3410J-304 | 制造商:Texas Instruments 功能描述:ISDN LINE INTERFACE, BASIC, 28 Pin, Ceramic, DIP |
| TP3410J304/NOPB | 功能描述:IC TRANSCEIVER MONOLITHIC 28CDIP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| TP3410J304-X | 功能描述:IC TXRX ISDN BASIC ACC 28-CERDIP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| TP3410N304 | 制造商:OC White Company 功能描述:ISDN U HDLC Interface 1-Line 160Kbps 5V 28-Pin CDIP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。