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參數(shù)資料
| 型號： | TP3410J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver |
| 中文描述： | DATACOM, DIGITAL SLIC, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數(shù)： | 22/32頁 |
| 文件大?。?/td> | 436K |
| 代理商： | TP3410J |
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Functional Description
(Continued)
The RXM4 Register consists of 8 bits, which correspond to
the M4 overhead bit position in each of the 8 Basic Frames
of a superframe. When the line is fully superframe synchro-
nized, the device extracts from the M channel these 8 bits
every superframe. At the end of each superframe, the regis-
ter content is sent to the Interrupt stack, in accordance with
the validation mode selected in Register OPR. M41, and
M42 in NT mode, are only provided via this register while
the line is fully activated (after AI). During the activation and
deactivation sequences the ‘‘a(chǎn)ct’’ and ‘‘dea’’ bits are pro-
cessed automatically, see the Activation Control section.
10.4 RXM56: Receive M5/M6 Spare Bits Status Register
This register is significant only when the Spare Bit process-
ing is enabled (see register OPR).
Byte 2
7
6
5
4
3
2
1
0
0
ES2
ES1
M51
M61
M52
RFB
NEB
Data in this register consists of 7 bits: M51, M52, M61 and
RFB (RFB
e
receive febe, the far-end block-error indicator
from the M62 bit position), all of which correspond to the
overhead bits received once per superframe, plus NEB,
which is an internally generated bit indicating a near-end
block-error. Bits ES1 and ES2 are available in GCI mode
only. When the line is fully superframe synchronized, the
device loads the register with the received bits M51, M52,
M61 and febe every superframe; in GCI mode the ES1 and
ES2 input pins are also sampled. The 12-bit crc received
from the far-end is also compared at the end of the super-
frame with the crc previously calculated by the device. If an
error is detected, the febe bit in the transmit direction is
automatically forced low in the next superframe and the
NEB bit in this register is set low also. The register content
is sent to the Interrupt stack at the end of each superframe.
10.5 Block Error Counter: BEC1
Byte 2
7
6
5
4
3
2
1
0
ec7
ec6
ec5
ec4
ec3
ec2
ec1
ec0
At Power-On Reset this counter is preset
e
X
ê
FF.
BEC1
This 8-bit counter is decremented by 1, starting from the
value in the ECT1 register, if either febe
e
0 or nebe
e
0 in
the same superframe. When the counter reaches X’00 (and
if the Interrupt is enabled by means of the EIE bit in Register
OPR), an interrupt is queued in the interrupt stack. The
counter may also be read at any time; the count will be the
ECT1 value minus the number of errors since the last read
of this register. Reading the counter, or when the counter
decrements to X
ê
00, causes the count to be reset to the
ECT1 value.
11.0 ACTIVATION/DEACTIVATION
A common coding table is used for the commands in the
Activation Control Register and the status indicators in the
Activation Indication Register. They control the Power-Up/
Down, Activation and Deactivation states of the device.
When the device is in GCI Mode, the 4 significant bits in
these registers (3–0) continuously report their current con-
tents in the C/I channel. In Microwire Mode the registers are
addressed with a normal 16-bit cycle as shown in Table II.
11.1 Activation Control Register
Byte 2
7
6
5
4
3
2
1
0
0
0
0
0
C4
C3
C2
C1
At Power-On Reset, and each time the device is Deactivat-
ed (or an Activation attempt fails), this register is initialized
to X
ê
0F.
Activation commands and status indicators are coded as
follows:
CODE
LT MODE
NT MODE
C4
C3
C2
C1
IND
COM
IND
COM
0
0
0
0
TIM
*
PUP/DR
DP/LSD
PUP
0
0
0
1
X
RES
X
RES
0
1
0
0
EI
FA0
EI
SEI
0
1
0
1
X
PDN
X
PDN
0
1
1
0
SYNC
X
X
X
1
0
0
0
AP
AR
AP
AR
1
1
0
0
AI
AC
DC
*
AI
AC
DC
*
1
1
1
1
DI
DI
Note 1:
X indicates reserved codes which should not be used.
11.2 Activation Commands
PUP
This command powers up the device and starts
the oscillator.
PUP/DR When the TP3410 is in the power-down state, this
command powers up the device and starts the
oscillator. In LT mode only, when the device is
activated, this code is a Deactivation Request,
which forces the device through the specified de-
activation sequence by setting ‘‘dea’’
e
0 in 4 con-
secutive superframes before ceasing transmis-
sion.
PDN
This power-down command immediately forces
the device to a low power state, without sequenc-
ing through any of the de-activation states. It
should normally only be used after the TP3410
has been put in a known state, e.g., after a DI
status indication has been reported.
AR
Activation Request, which is used after first pow-
ering up the device to initiate the specified Activa-
tion sequence.
AC
Activation Complete, which may be used to set
‘‘a(chǎn)ct’’
e
1 in each direction at the completion of
activation. In LT mode this is only necessary if
Breakpoint 2 is enabled (in Register CR2); in NT
mode this is normally required when synchroniza-
tion on the S/T Interface is confirmed by detec-
tion of INFO3.
RES
RES is the reset command which resets the acti-
vation sequencer to the Receive Reset state and
resets the DSP coefficients in preparation for a
cold-start. This command should be used only in
the event of a failed activation attempt (expiry of
T4 or T5); it does not affect the Command Regis-
ters.
22
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