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參數(shù)資料
| 型號： | TP3410J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver |
| 中文描述： | DATACOM, DIGITAL SLIC, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數(shù)： | 21/32頁 |
| 文件大?。?/td> | 436K |
| 代理商： | TP3410J |
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Functional Description
(Continued)
9.12 Transmit M5/M6 Spare Bits Register TXM56
(Write Only)
Byte 2
7
6
5
4
3
2
1
0
0
0
LEC
M51
M61
M52
TFB
CTC
At Power-On Reset, and each time the device is Deactivat-
ed (or an Activation attempt fails), this register is initialized
to X
ê
1E.
M51, M61, M52
The M51, M61, and M52 bits in this register control the ap-
propriate overhead bits transmitted to the line. They should
be set
e
1 but may be subject to future standardization.
Transmit febe Bit Control: TFB
This bit should normally be set
e
1. The febe bit transmitted
in the M62 bit position is then automatically controlled by
the device; febe is the far-end block error bit which is nor-
mally high, and set low when a crc (cyclic redundancy
check) error has been detected in the previously received
superframe. For test purposes, however, febe may be
forced continuously low by setting TFB
e
0.
Corrupt Transmit crc: CTC
To allow the normal calculation of the crc for the transmitted
data to the line, set CTC
e
0. In order to send a corrupted
crc for test purposes, set CTC
e
1, which causes the crc
result to be continuously inverted prior to transmission.
Latched External Control: LEC
This bit directly controls the LEC output pin, in GCI mode.
9.13 Transmit EOC Register
(Write Only)
When the line is fully superframe synchronized, the device
continuously sends the contents of this register to the line
twice per superframe in the EOC channel field. The register
contents are loaded into the line transmit register every half
superframe.
Byte 1
Byte 2
3
2
1
0
7
6
5
4
3
2
1
0
ea1 ea2 ea3 dm ei1 ei2 ei3 ei4 ei5 ei6 ei7 ei8
At Power-On Reset, and each time the device is Deactivat-
ed (or an Activation attempt fails), this register is initialized
to X
ê
FF.
The Tx EOC Register contains 12 bits which correspond to
the 12 bits of a message in the Embedded Operations
Channel, see Table I:
ea1, ea2 and ea3 correspond to the 3 EOC destination ad-
dress bits, eoca1, eoca2, eoca3;
the dm bit indicates if the information is in message mode or
data mode (data if dm
e
0, message if dm
e
1);
ei1–ei8 correspond to the 8 eoc data bits, eoci1–eoci8.
Only bits 7–4 of byte 1 are used to address this register, as
shown in Table II.
9.14 Error Counter Threshold Register: ECT1
Byte 2
7
6
5
4
3
2
1
0
O7
O6
O5
O4
O3
O2
O1
O0
At Power-On Reset this register is initialized to X
ê
FF.
This register may be loaded with any value, which is then
used to preset the Block Error Counter BEC1. BEC1 decre-
ments 1 count for each block error. When the counter value
reaches X’00 the BEC1 interrupt is sent to the stack (if en-
abled by EIE
e
1 in the OPR reg.).
10.0 STATUS REGISTERS
All Status Register addressing and bit-level functions are
the same for both the Microwire and GCI Monitor Channels,
except where noted. Register addresses are listed in Table
III.
10.1 Reading Status Registers In Response To An
Interrupt
Conditions occurring in the device which generate Microwire
interrupts or GCI Monitor Channel messages are queued in
a stack, with a pre-defined priority, see Table III. In Micro-
wire mode the INT pin is pulled low and a NOP command
should be loaded into the Microwire during the read cycle
(or a valid command may be used to modify a register if
required). In GCI mode, the interrupt stack generates an
autonomous one-way message in the Monitor Channel.
10.2 Receive EOC Register
This register is significant only when the EOC channel pro-
cessing is enabled (see register OPR).
Byte 1
Byte 2
3
2
1
0
7
6
5
4
3
2
1
0
ea1 ea2 ea3 dm ei1 ei2 ei3 ei4 ei5 ei6 ei7 ei8
The RX EOC Register contains 12 bits which correspond to
the 12 bits of a message in the Embedded Operations
Channel, see Table I: ea1, ea2 and ea3 correspond to the 3
EOC destination address bits, eoca1, eoca2, eoca3;
the dm bit indicates if the information is in message mode or
data mode;
ei1–ei8 correspond to the 8 eoc data bits, eoci1–eoci8.
Only bits 7–4 of byte 1 are used to address this register, as
shown in Table II.
When the line is fully superframe synchronized, the device
extracts these 12 bits from the channel every half super-
frame. Each EOC message is validated according to the
mode selected in Register OPR, and if a message contains
a new address or new data, the Rx EOC Register is sent to
the Control Interface, through an interrupt cycle request. If
one of the defined coded commands is received, e.g., Send
Corrupted CRC, then the appropriate Command Register
instruction must be written to the device to select that func-
tion.
10.3 RXM4: Receive M4 Overhead Bits Register
This register is significant only when the Spare Bit process-
ing is enabled (see register OPR).
Byte 2
7
6
5
4
3
2
1
0
M41
M42
M43
M44
M45
M46
M47
M48
21
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