參數(shù)資料
型號(hào)： TMS45160P
廠(chǎng)商： Texas Instruments, Inc.
英文描述： 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
中文描述： 262144字由16位高速動(dòng)態(tài)隨機(jī)存取記憶體
文件頁(yè)數(shù)： 9/23頁(yè)
文件大?。?/td> 353K
代理商： TMS45160P
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued) (see Note 5)
’45160-60
’45160P-60
’45160-70
’45160P-70
’45160-80
’45160P-80
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tCAH
tDHR
tDH
tAR
tRAH
tRCH
tRRH
tWCH
tWCR
tCLCH
tAWD
tCHR
tCRP
tCSH
tCSR
tCWD
tOEH
tOED
tROH
tRAD
tRAL
tCAL
tRCD
tRPC
tRSH
tRWD
tCPR
tRPS
tRASS
tCHS
Hold time, column address after xCAS low (see Note 10)
10
15
15
ns
Hold time, data after RAS low (see Note 12)
30
35
35
ns
Hold time, data after xCAS low (see Note 10)
10
15
15
ns
Hold time, column address after RAS low (see Note 12)
30
35
35
ns
Hold time, row address after RAS low
10
10
10
ns
Hold time, read after xCAS high (see Note 13)
0
0
0
ns
Hold time, read after RAS high (see Note 13)
0
0
0
ns
Hold time, write after xCAS low (see Note 13)
10
15
15
ns
Hold time, write after RAS low (see Note 14)
30
35
35
ns
Hold time, xCAS low to xCAS high
5
5
5
ns
Delay time, column address to W low (see Note 15)
55
65
70
ns
Delay time, RAS low to xCAS high (see Note 11)
15
15
20
ns
Delay time, xCAS high to RAS low
0
0
0
ns
Delay time, RAS low to xCAS high
60
70
80
ns
Delay time, xCAS low to RAS low (see Note 11)
10
10
10
ns
Delay time, xCAS low to W low (see Note 15)
40
50
50
ns
Hold time, OE command
15
20
20
ns
Delay time, OE high before data at DQ
15
20
20
ns
Delay time, OE low to RAS high
10
10
10
ns
Delay time, RAS low to column address (see Note 16)
15
30
15
35
15
40
ns
Delay time, column address to RAS high
30
35
40
ns
Delay time, column address to xCAS high
30
35
40
ns
Delay time, RAS low to xCAS low (see Note 16)
20
45
20
50
20
60
ns
Delay time, RAS high to xCAS low (see Note 11)
0
0
0
ns
Delay time, xCAS low to RAS high
15
20
20
ns
Delay time, RAS low to W low (see Note 15)
85
100
110
ns
Pulse duration, xCAS precharge before self refresh
0
0
0
ns
Pulse duration, RAS precharge after self refresh
110
130
150
ns
μ
s
ns
Pulse duration, self refresh entry from RAS low
100
100
100
Hold time, xCAS low after RAS high (for self refresh)
– 50
– 50
– 50
tREF
Refresh time interval
’45160
8
8
8
ms
’45160P
64
64
64
tT
Transition time
2
50
2
50
2
50
ns
NOTES:
5. Timing measurements are referenced to VIL max and VIH min.
10. Referenced in the later of xCAS or W in write operations.
11. Early-write operation only
12. The minimum value is measured when tRCD is set to tRCD min as a reference.
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. xCBR refresh only
15. Read-modify-write operation only
16. Maximum value specified only to assure access time
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