參數(shù)資料
型號(hào)： TMS45160P
廠商： Texas Instruments, Inc.
英文描述： 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES
中文描述： 262144字由16位高速動(dòng)態(tài)隨機(jī)存取記憶體
文件頁(yè)數(shù)： 17/23頁(yè)
文件大?。?/td> 353K
代理商： TMS45160P
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
RAS
UCAS
A0–A8
W
OE
Column
tRASP
Column
Row
Valid Out
tOEA
Valid In
Valid In
Valid Out
tRP
tCRP
tRSH
tCP
tCSH
tPRWC
tCAS
tRCD
tASR
tASC
tCAH
tCWD
tAWD
tRWD
tWP
tCWL
tRWL
tRAH
tCAC
(see Note B)
tCPA
tOEH
tOED
tOEH
tOEZ
tAA
tRAC
tRCS
See Note C
tDS
tCLZ
LCAS
tCLCH
tRAD
DQ0–DQ15
(see Note A)
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. tCAC is measured from xCAS to its corresponding DQx.
C. Output can go from the high-impedance state to an invalid data state prior to the specified access time.
D. xCAS order is arbitrary.
E. A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write cycle timing specifications are
not violated.
Figure 8. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing
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