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參數(shù)資料
| 型號： | TMS45160P |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 262144字由16位高速動態(tài)隨機(jī)存取記憶體 |
| 文件頁數(shù)： | 3/23頁 |
| 文件大?。?/td> | 353K |
| 代理商： | TMS45160P |
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
data in (DQ0–DQ15)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to xCAS
and the data is strobed in by the first occurring xCAS with setup and hold times referenced to data in. In a
delayed-write or read-modify-write cycle, xCAS is already low and the data is strobed in by W with setup and
hold times referenced to data in. In a delayed-write or read-modify-write cycle, OE must be high to bring the
output buffers to the high-impedance state prior to impressing data on the I/O lines.
data out (DQ0–DQ15)
The 3-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating)
state until xCAS and OE are brought low. In a read cycle, the output becomes valid after the access-time interval
t
CAC
(which begins with the negative transition of xCAS) as long as t
RAC
and t
AA
are satisfied.
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance
state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and xCAS to be brought low for the output buffers to go into the
low-impedance state. They remain in the low-impedance state until either OE or xCAS is brought high.
RAS-only refresh
A refresh operation must be performed at least once every 8 ms (64 ms for TMS45160P) to retain data. This
can be achieved by strobing each of the 512 rows (A0–A8). A normal read or write cycle refreshes all bits in
each row that is selected. A RAS-only operation can be used by holding all xCAS at the high (inactive) level,
conserving power as the output buffers remain in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh.
hidden refresh
Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding
xCAS at V
IL
after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle. The external address is ignored and the refresh address is generated internally.
xCAS-before-RAS (xCBR) refresh
xCBR refresh is utilized by bringing at least one xCAS low earlier than RAS (see parameter t
CSR
) and holding
it low after RAS falls (see parameter t
CHR
). For successive xCBR refresh cycles, xCAS can remain low while
cycling RAS. The external address is ignored and the refresh address is generated internally.
A low-power battery-backup refresh mode that requires less than 500-
μ
A refresh current is available on the
TMS45160P. Data integrity is maintained using xCBR refresh with a period of 125
μ
s holding
RAS low for less than 1
μ
s. To minimize current consumption, all input levels must be at CMOS levels
(V
IL
≤
0.2 V, V
IH
≥
V
CC
– 0.2 V).
self refresh (TMS45160P)
The self-refresh mode is entered by dropping xCAS low prior to RAS going low. Then xCAS and RAS are both
held low for a minimum of 100
μ
s. The chip is refreshed internally by an on-board oscillator. No external address
is required since the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS
and xCAS are brought high to satisfy t
CHS
. Upon exiting the self-refresh mode, a burst refresh (refresh a full set
of row addresses) must be executed before continuing with normal operation. This ensures that the DRAM is
fully refreshed.
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