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參數(shù)資料
| 型號： | TMS45160P |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 262144字由16位高速動態(tài)隨機(jī)存取記憶體 |
| 文件頁數(shù)： | 15/23頁 |
| 文件大?。?/td> | 353K |
| 代理商： | TMS45160P |
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
Don’t
Care
Don’t Care
Valid
Out
Valid
Out
Valid
Out
RAS
UCAS
A0–A8
W
DQ8–DQ15
DQ0–DQ7
OE
Column
Column
tRASP
tRCD
tCRP
tRP
tRSH
tPC
tCP
tASR
tRAH
tAR
tASC
tCAH
tCAL
tRAL
tRAD
tRCH
tRRH
tOFF
tOEZ
tRCS
tAA
tRAC
tAA
tOEA
LCAS
Row
Don’t Care
tCAC
(see Note A)
Don’t
Care
tCPA
tCAS
tCLZ
See Note B
tCSH
NOTES: A. tCAC is measured from xCAS to its corresponding DQx.
B. Access time is tCPA or tAA dependent.
C. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
D. xCAS order is arbitrary.
E. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
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