參數(shù)資料
型號： TMS32C5402PGER10G4
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSOR
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 59/68頁
文件大?。?/td> 948K
代理商： TMS32C5402PGER10G4
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
59
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
multichannel buffered serial port timing (continued)
timing requirements for McBSP as SPI master or slave: [H=0.5t
c(CO)
] CLKSTP = 10b, CLKXP = 1
(see Figure 33)
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
tsu(BDRV-BCKXH)
th(BCKXH-BDRV)
tsu(BFXL-BCKXL)
tc(BCKX)
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Setup time, BDR valid before BCLKX high
12
2 – 12H
ns
Hold time, BDR valid after BCLKX high
4
5 + 12H
ns
Setup time, BFSX low before BCLKX low
10
ns
Cycle time, BCLKX
12H
32H
ns
switching characteristics for McBSP as SPI master or slave: [H=0.5t
c(CO)
] CLKSTP = 10b,
CLKXP = 1
(see Figure 33)
PARAMETER
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
th(BCKXH-BFXL)
td(BFXL-BCKXL)
td(BCKXL-BDXV)
Hold time, BFSX low after BCLKX high§
Delay time, BFSX low to BCLKX low
T – 3
T + 4
ns
D – 5
D + 3
ns
Delay time, BCLKX low to BDX valid
–2
6
6H + 5
10H + 15
ns
tdis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX high
D – 2
D + 3
ns
tdis(BFXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
2H + 3
6H + 17
ns
td(BFXL-BDXV)
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T =
BCLKX period = (1 + CLKGDV) * 2H
D =
BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
Delay time, BFSX low to BDX valid
4H – 2
8H + 17
ns
tsu(BFXL-BCKXL)
th(BCKXH-BDRV)
tdis(BFXH-BDXHZ)
tdis(BCKXH-BDXHZ)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
BCLKX
BFSX
BDX
BDR
td(BFXL-BCKXL)
td(BFXL-BDXV)
td(BCKXL-BDXV)
tsu(BDRV-BCKXH)
th(BCKXH-BFXL)
LSB
MSB
tc(BCKX)
Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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