參數(shù)資料
型號： TMS32C5402PGER10G4
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSOR
中文描述： 定點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 19/68頁
文件大?。?/td> 948K
代理商： TMS32C5402PGER10G4
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
19
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
parallel I/O ports
The ’5402 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW
instruction. The IS signal indicates a read/write operation through an I/O port. The ’5402 can interface easily
with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.
enhanced 8-bit host-port interface
The ’5402 host-port interface, also referred to as the HPI8, is an enhanced version of the standard 8-bit HPI
found on earlier ’54x DSPs (’542, ’545, ’548, and ’549). The HPI8 is an 8-bit parallel port for interprocessor
communication. The features of the HPI8 include:
Standard features:
Sequential transfers (with autoincrement) or random-access transfers
Host interrupt and ’54x interrupt capability
Multiple data strobes and control pins for interface flexibility
Enhanced features of the ’5402 HPI8:
Access to entire on-chip RAM through DMA bus
Capability to continue transferring during emulation stop
The HPI8 functions as a slave and enables the host processor to access the on-chip memory of the ’5402. A
major enhancement to the ’5402 HPI over previous versions is that it allows host access to the entire on-chip
memory range of the DSP. The HPI8 memory map is identical to that of the DMA controller shown in Figure 7.
The host and the DSP both have access to the on-chip RAM at all times and host accesses are always
synchronized to the DSP clock. If the host and the DSP contend for access to the same location, the host has
priority, and the DSP waits for one HPI8 cycle. Note that since host accesses are always synchronized to the
’5402 clock, an active input clock (CLKIN) is required for HPI8 accesses during IDLE states, and host accesses
are not allowed while the ’5402 reset pin is asserted.
The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers
are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with
the HPI8 through three dedicated registers — HPI address register (HPIA), HPI data register (HPID), and an
HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register
is accessible by both the host and the ’5402.
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