- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385001 > TMS32C5402PGER10G4 (Texas Instruments, Inc.) FIXED-POINT DIGITAL SIGNAL PROCESSOR PDF資料下載
參數(shù)資料
| 型號(hào)： | TMS32C5402PGER10G4 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 50/68頁(yè) |
| 文件大?。?/td> | 948K |
| 代理商： | TMS32C5402PGER10G4 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)當(dāng)前第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
50
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
reset, BIO, interrupt, and
MP/MC timings
timing requirements for reset, BIO, interrupt, and MP/MC
[H = 0.5 t
c(CO)
] (see Figure 22, Figure 23,
and Figure 24)
MIN
MAX
UNIT
ns
th(RS)
th(BIO)
th(INT)
th(MPMC)
tw(RSL)
tw(BIO)S
tw(BIO)A
tw(INTH)S
tw(INTH)A
tw(INTL)S
tw(INTL)A
tw(INTL)WKP
tsu(RS)
tsu(BIO)
tsu(INT)
tsu(MPMC)
The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is
corresponding to three CLKOUT sampling sequences.
If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50
μ
s to ensure
synchronization and lock-in of the PLL.
§Note that RS may cause a change in clock frequency, therefore changing the value of H.
Divide-by-two mode
Hold time, RS after CLKOUT low
0
Hold time, BIO after CLKOUT low
Hold time, INTn, NMI, after CLKOUT low
0
ns
0
ns
Hold time, MP/MC after CLKOUT low
Pulse duration, RS low§
0
ns
4H+5
ns
Pulse duration, BIO low, synchronous
2H+2
ns
Pulse duration, BIO low, asynchronous
4H
ns
Pulse duration, INTn, NMI high (synchronous)
2H
ns
Pulse duration, INTn, NMI high (asynchronous)
4H
ns
Pulse duration, INTn, NMI low (synchronous)
2H+2
ns
Pulse duration, INTn, NMI low (asynchronous)
4H
ns
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
Setup time, RS before X2/CLKIN low
10
ns
5
ns
Setup time, BIO before CLKOUT low
7
10
ns
Setup time, INTn, NMI, RS before CLKOUT low
7
10
ns
Setup time, MP/MC before CLKOUT low
5
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMS34020 | GRAPHICS PROCESSORS |
| TMS3450NL | LED DUPLEX DIGITAL RADIO CLOCK |
| TMS3471CFS | 780- 】 488-pixel ccd image sensor |
| TMS3471 | 2/3-INCH NTSC TIMER |
| TMS3473 | PARALLEL DRIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS32C6202BGNZA250 | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS32C6203BGLS173A | 制造商:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR - Trays |
| TMS32C6203BGLS173H | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:DSP FIX PT 16BIT 173MHZ 1384MIPS 384PIN FC/CSP - Trays |
| TMS32C6203BGNY17-3 | 制造商:Texas Instruments 功能描述:TMS C6203B 1.7V REV 2.X GNY 300 MHZ - Trays |
| TMS32C6203BGNZA250 | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Fixed-Point Dig Sig Processor RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。