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參數(shù)資料
| 型號： | TMS32C5402PGER10G4 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 定點數(shù)字信號處理器 |
| 文件頁數(shù)： | 24/68頁 |
| 文件大小： | 948K |
| 代理商： | TMS32C5402PGER10G4 |
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
DMA priority level
Each DMA channel can be independently assigned high priority or low priority relative to each other. Multiple
DMA channels that are assigned to the same priority level are handled in a round-robin manner.
DMA source/destination address modification
The DMA provides flexible address-indexing modes for easy implementation of data management schemes
such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and
can be post-incremented, post-decremented, or post-incremented with a specified index offset.
DMA in autoinitialization mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers can
be preloaded for the next block transfer through the DMA global reload registers (DMGSA, DMGDA, and
DMGCR). Autoinitialization allows:
Continuous operation:
Normally, the CPU would have to reinitialize the DMA immediately after the
completion of the current block transfer; but with the global reload registers, it can reinitialize these values
for the next block transfer any time after the current block transfer begins.
Repetitive operation:
The CPU does not preload the global reload register with new values for each block
transfer but only loads them on the first block transfer.
DMA transfer counting
The DMA channel element count register (DMCTRx) and the frame count register (DMSFCx) contain bit fields
that represent the number of frames and the number of elements per frame to be transferred.
Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum number
of frames per block transfer is 128 (FRAME COUNT= 0ffh). The counter is decremented upon the last read
transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is reloaded with
the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count of 0 (default
value) means the block transfer contains a single frame.
Element count. This 16-bit value defines the number of elements per frame. This counter is decremented
after the read transfer of each element. The maximum number of elements per frame is 65536
(DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter is reloaded
with the DMA global count reload register (DMGCR).
DMA transfers in double-word mode
Double-word mode allows the DMA to transfer 32-bit words in any index mode. In double-word mode, two
consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated
following each transfer. In this mode, each 32-bit word is considered to be one element.
DMA channel index registers
The particular DMA channel index register is selected by way of the SIND and DIND field in the DMA mode
control register (DMMCRx). Unlike basic address adjustment, in conjunction with the frame index DMFRI0 and
DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer is
the last in the current frame. The normal adjustment value (element index) is contained in the element index
registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame, is determined by
the selected DMA frame index register, either DMFRI0 or DMFRI1.
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