參數(shù)資料
型號： TMS32C5402PGER10G4
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSOR
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 54/68頁
文件大小： 948K
代理商： TMS32C5402PGER10G4
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
54
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
multichannel buffered serial port timing
timing requirements for McBSP [H=0.5t
c(CO)
]
(see Figure 28 and Figure 29)
MIN
MAX
UNIT
tc(BCKRX)
tw(BCKRX)
Cycle time, BCLKR/X
BCLKR/X ext
4H
ns
Pulse duration, BCLKR/X high or BCLKR/X low
BCLKR/X ext
2H–2
ns
tsu(BFRH-BCKRL)
Setup time external BFSR high before BCLKR low
Setup time, external BFSR high before BCLKR low
BCLKR int
8
ns
BCLKR ext
1
th(BCKRL-BFRH)
Hold time external BFSR high after BCLKR low
Hold time, external BFSR high after BCLKR low
BCLKR int
0
ns
BCLKR ext
3
tsu(BDRV-BCKRL)
Setup time BDR valid before BCLKR low
Setup time, BDR valid before BCLKR low
BCLKR int
5
ns
BCLKR ext
0
th(BCKRL-BDRV)
Hold time BDR valid after BCLKR low
Hold time, BDR valid after BCLKR low
BCLKR int
0
ns
BCLKR ext
4
tsu(BFXH-BCKXL)
Setup time external BFSX high before BCLKX low
Setup time, external BFSX high before BCLKX low
BCLKX int
7
ns
BCLKX ext
0
th(BCKXL-BFXH)
Hold time external BFSX high after BCLKX low
Hold time, external BFSX high after BCLKX low
BCLKX int
0
ns
BCLKX ext
3
tr(BCKRX)
tf(BCKRX)
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Rise time, BCKR/X
BCLKR/X ext
8
ns
Fall time, BCKR/X
BCLKR/X ext
8
ns
switching characteristics for McBSP [H=0.5t
c(CO)
]
(see Figure 28 and Figure 29)
PARAMETER
MIN
MAX
UNIT
tc(BCKRX)
tw(BCKRXH)
tw(BCKRXL)
Cycle time, BCLKR/X
BCLKR/X int
4H
ns
Pulse duration, BCLKR/X high
BCLKR/X int
D – 2
C – 2
D + 2
C + 2
ns
Pulse duration, BCLKR/X low
BCLKR/X int
ns
td(BCKRH-BFRV)
Delay time BCLKR high to internal BFSR valid
Delay time, BCLKR high to internal BFSR valid
BCLKR int
–2
2
ns
BCLKR ext
3
9
ns
td(BCKXH-BFXV)
Delay time BCLKX high to internal BFSX valid
Delay time, BCLKX high to internal BFSX valid
BCLKX int
0
4
ns
BCLKX ext
8
11
tdis(BCKXH-BDXHZ)
Disable time, BCLKX high to BDX high impedance following last data
Disable time, BCLKX high to BDX high im edance following last data
bit of transfer
BCLKX int
–1
4
ns
BCLKX ext
3
9
td(BCKXH-BDXV)
Delay time BCLKX high to BDX valid
Delay time, BCLKX high to BDX valid
DXENA = 0§
BCLKX int
0
7
ns
BCLKX ext
3
11
td(BFXH-BDXV)
Delay time, BFSX high to BDX valid
BFSX int
–1
3
ns
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
T =
BCLKRX period = (1 + CLKGDV) * 2H
C =
BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D =
BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§The transmit delay enable (DXENA) and A–bis mode (ABIS) features of the McBSP are not implemented on the TMS320VC5402.
Minimum delay times also represent minimum output hold times.
BFSX ext
3
13
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