
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
TABLE OF CONTENTS
Description
Pin Assignments
Terminal Functions
Memory
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On-Chip Peripherals
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Software-Programmable Wait-State Generator
Programmable Bank-Switching Wait States
Parallel I/O Ports
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Enhanced 8-Bit Host-Port Interface
Multichannel Buffered Serial Ports
Hardware Timer
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Clock Generator
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DMA Controller
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Memory-Mapped Registers
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McBSP Control Registers And Subaddresses
DMA Subbank Addressed Registers
Interrupts
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3
6
7
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12
16
16
18
19
19
20
21
21
23
27
29
29
31
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Documentation Support
Absolute Maximum Ratings
Recommended Operating Conditions
Electrical Characteristics
Parameter Measurement Information
Internal Oscillator With External Crystal
Divide-By-Two Clock Option (PLL Disabled)
Multiply-By-N Clock Option
Memory and Parallel I/O Interface Timing
Ready Timing For Externally Generated Wait States
HOLD and HOLDA Timings
Reset, BIO, Interrupt, and MP/MC Timings
Instruction Acquisition (IAQ), Interrupt Acknowledge
(IACK), External Flag (XF), and TOUT Timings
Multichannel Buffered Serial Port Timing
HPI8 Timing
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Mechanical Data
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33
34
34
35
35
36
37
38
39
45
49
50
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52
54
61
65
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REVISION HISTORY
REVISION
DATE
PRODUCT STATUS
HIGHLIGHTS
*
October 1998
Advanced Information
Original
A
April 1999
Advanced Information
Revised to update characteristic data
B
July 1999
Advanced Information
Revised to update characteristic data
C
September 1999
Advanced Information
Revised to update characteristic data
D
January 2000
Production Data
Revised to release production data.
E
August 2000
Production Data
Added Table of Contents, Revision History, and corrected IDLE3
current on page 35.