參數(shù)資料
型號(hào)： T7264
廠商： Lineage Power
英文描述： U-Interface 2B1Q Transceiver(U接口 2B1Q收發(fā)器)
中文描述： U型接口2B1Q收發(fā)器（ü接口2B1Q收發(fā)器）
文件頁(yè)數(shù)： 9/54頁(yè)
文件大?。?/td> 876K
代理商： T7264
Data Sheet
April 1998
T7264 U-Interface 2B1Q Transceiver
Lucent Technologies Inc.
9
Device Interface and Connections
(continued)
Reset Time
Reset time depends on the conditions under which the chip is reset. There are three cases to consider:
I
When the chip is initially powered on, the RESET pin must be held low (below 0.5 V) for 1.5 ms. This allows
1.0 ms for the oscillator start-up and 0.5 ms for the digital reset process. An additional 1.0 ms is needed to allow
the analog circuitry to fully power up before the chip becomes fully functional.
I
When the chip is in the idle mode, a software or hardware reset, applied for a minimum of three K2 frames, starts
the reset process. As before, the analog circuitry requires an additional 1.0 ms before the chip becomes fully
functional.
I
If the chip is already fully powered up and functional, a software or hardware reset, applied for a minimum of
three K2 frames, is sufficient to complete the reset process.
When the chip is in the reset state, the output of the line driver is at 0 V and the transmit data is also 0 V.
5-5165a
Figure 6. RESET Waveform Normal Operation
5-5166a
Figure 7. RESET Timing for Synchronized Clocks
RESET PIN
INTERNAL RESET
(AFTER SCHMITT
TRIGGER)
t
t
DEVICE REACHES POWER-ON
MODE (FULLY FUNCTIONAL)
4.75 V
POWER SUPPLY VOLTAGE
1.5 ms MIN
1.0 ms
0 0 1
4.75 V
POWER SUPPLY VOLTAGE
RESET PIN
1
NORMAL
RESET
AS IN FIGURE 6
UNDEFINED
UNDEFINED
1 MCLK PERIOD
2 MCLK PERIODS
F
C
≥
2.5 ms
≥
3 K2
FRAMES
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