參數(shù)資料
型號(hào): T7264
廠商: Lineage Power
英文描述: U-Interface 2B1Q Transceiver(U接口 2B1Q收發(fā)器)
中文描述: U型接口2B1Q收發(fā)器(ü接口2B1Q收發(fā)器)
文件頁數(shù): 32/54頁
文件大小: 876K
代理商: T7264
32
Lucent Technologies Inc.
Data Sheet
April 1998
T7264 U-Interface 2B1Q Transceiver
Activation and the K2 Interface
(continued)
5-5180
Notes:
T0
T1
T2
T3
T4
T5
T6
T7
Reset state.
Network and NT are awake.
NT discontinues transmission, indicating that the NT is ready to receive signal.
Network responds to termination of signal and begins transmitting signal toward the NT.
Network begins transmitting SL2 toward the NT, indicating that the network is ready to receive SN2.
NT begins transmitting SN2 toward the network, indicating that NT has acquired SW frame and detected SL2.
NT has acquired superframe marker, and is fully operational.
Network has acquired superframe marker, and is fully operational.
Figure 21. State Sequence for DSL Transceiver Start-Up
Applications
The T7264 is intended for use in both switch and customer premises equipment including a central office (CO), a
private branch exchange (PBX), a 2-wire to 4-wire converter (NT1), and terminal equipment (TE). The physical ter-
mination of the U-interface at the network end is referred to as the line termination (LT); the physical termination at
the user end is referred to as the network termination (NT). Figure 22 shows a loop configuration using several U-
interface devices at various locations.
The T7264 provides system access to the U loop through the K2 interface. The K2 interface is a TDM serial interface
which provides access to 2B+D data, U-interface maintenance, and T7264 device control/status.
Figure 23 shows a 2-wire terminal application with the T7264 providing the U-interface. The T7270 provides the
microprocessor with access to the individual octets of the K2 data stream. The B1 and B2 data could be transferred
to either a codec for voice communications, such as the T7513A, or to an HDLC controller for data communications,
such as the T7121. Another T7121 could provide microprocessor access to D-channel HDLC processing. The
microprocessor would control initialization, activation/deactivation, D-channel processing, and maintenance func-
tions.
A
B
C
D
A + C
5 s FOR COLD START
A + C
150 ms FOR WARM START
B + D
10 s FOR COLD START
B + D
150 ms FOR WARM START
4 ms
480 ms
T0
T1
T5
TN
SN1
(OP-
TIONAL)
6
FRAMES
NT
NETWORK
NT
NETWORK
SL1 (OPTIONAL)
SL2
SL3
SN2
SN3
TL
2 FRAMES
T2
T3
T6
T7
T4
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