參數(shù)資料
型號(hào): T7264
廠商: Lineage Power
英文描述: U-Interface 2B1Q Transceiver(U接口 2B1Q收發(fā)器)
中文描述: U型接口2B1Q收發(fā)器(ü接口2B1Q收發(fā)器)
文件頁(yè)數(shù): 36/54頁(yè)
文件大?。?/td> 876K
代理商: T7264
36
Lucent Technologies Inc.
Data Sheet
April 1998
T7264 U-Interface 2B1Q Transceiver
Electrical Characteristics
(continued)
Table 27. Internal PLL Characteristics
* Set by digital PLL; therefore, variations track MTC (LT mode) or U-interface line rate (NT mode).
Table 28. Digital dc Characteristics (Over Operating Ranges)
Loop-Range Performance Characteristics
The T7264 transceiver is designed to allow systems to meet the loop-range requirements of ANSI Standard T1.601-
1992 when the transceiver is used with the proper peripheral circuitry.
The line driver provides pulses that produce the 2.5 V template required of the T1.601 specification when connected
to the proper transformer and interface circuitry.
Parameter
Test Conditions
–3 dB point (LT)
–3 dB point (NT), 18 kft 26 AWG
at 0.15 Hz typical (LT)
at 1.5 Hz typical (NT)
Min
±
250
Typ
0.45*
5*
0.4*
1.0*
Max
Unit
ppm
Hz
Hz
dB
dB
Total Pull Range
Jitter Transfer Function
Jitter Peaking
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Leakage Current:
Low
High
Low
High
Input Voltage:
Low
High
Low-to-High Threshold
High-to-Low Threshold
Low
High
Output Leakage:
Low
High
Output Leakage:
Low, TTL
I
IL
I
IH
I
ILpu
I
IHpu
V
IL
= 0 (pin 1, 2)
V
IH
= V
DD
(pin 1, 2)
V
IL
= 0 (pins 7—11, 14—15, 24—26)
V
IH
= V
DD
(pins 7—11, 14—15, 24—26)
–10
–52
10
–10
10
μ
A
μ
A
μ
A
μ
A
V
IL
V
IH
V
ILs
V
IHs
V
ILc
V
IHc
All Pins Except Pin 7, 10, 11, 24
All Pins Except Pin 7, 10, 11, 24
Pin 7
Pin 7
Pins 10, 11, 24
Pins 10, 11, 24
2.0
V
DD
– 0.5
0.7 V
DD
0.8
0.5
0.2 V
DD
V
V
V
V
V
V
I
OZL
I
OZH
V
OL
= 0; Pin 26 = 0
V
OH
= V
DD;
Pin 26 = 0
10
–10
μ
A
μ
A
High, TTL
V
OL
V
OH
I
OL
= 1.6 mA, Pins 3, 4, 5, 16
I
OL
= 3.3 mA, Pin 43
I
OL
= 6.5 mA, Pins 13, 23
I
OH
= 2.4 mA, Pins 3, 4, 5, 16
I
OH
= 5.1 mA, Pin 43
I
OH
= 10.4 mA, Pins 13, 23
2.4
2.4
2.4
0.4
0.4
0.4
V
V
V
V
V
V
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