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參數(shù)資料
| 型號： | T7264 |
| 廠商： | Lineage Power |
| 英文描述： | U-Interface 2B1Q Transceiver(U接口 2B1Q收發(fā)器) |
| 中文描述： | U型接口2B1Q收發(fā)器（ü接口2B1Q收發(fā)器） |
| 文件頁數(shù)： | 34/54頁 |
| 文件大小： | 876K |
| 代理商： | T7264 |
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34
Lucent Technologies Inc.
Data Sheet
April 1998
T7264 U-Interface 2B1Q Transceiver
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo-
sure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM)
and charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage
thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been
adopted for the CDM. However, a standard HBM (resistance = 1500
, capacitance = 100 pF) is widely used and,
therefore, can be used for comparison. The HBM ESD threshold presented here was obtained by using these cir-
cuit parameters:
Recommended Operating Conditions
* To meet ANSI T1.601 free-run line rate requirement, NT tolerance is 100 ppm.
x = tolerance of MTC.
Parameter
Min
–55
—
–0.5
—
Typ
—
—
—
—
Max
125
300
6.5
700
Unit
°
C
°
C
V
mW
Storage Temperature
Lead Temp (soldering or bonding)
Any Pin to GND
Power Dissipation (package limit)
ESD Threshold Voltage
Device
T7264-ML
Voltage
>500
Parameter
Symbol
T
A
V
DD
V
GG
CVR
MCLK
MCLK
Test Conditions
V
DD
= 5 V
±
5%
—
—
—
—
NT Mode
LT Mode
Min
–40
4.75
–10
0.08
—
–225*
–225 + x*
47
Typ
—
5.0
—
0.1
15.36
—
—
Max
85
5.25
10
0.2
—
225*
225 – x*
53
Unit
°
C
V
mV
μ
F
MHz
ppm
ppm
Ambient Temp
Any V
DD
GND to GND
Voltage Ref Capacitor
Master Clock Frequency
Master Clock Tolerance
Master Clock Duty Cycle
MCLK
—
—
%
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