參數(shù)資料
型號(hào)： T7264
廠商： Lineage Power
英文描述： U-Interface 2B1Q Transceiver(U接口 2B1Q收發(fā)器)
中文描述： U型接口2B1Q收發(fā)器（ü接口2B1Q收發(fā)器）
文件頁(yè)數(shù)： 11/54頁(yè)
文件大?。?/td> 876K
代理商： T7264
Lucent Technologies Inc.
11
Data Sheet
April 1998
T7264 U-Interface 2B1Q Transceiver
K2 Interface Description
The K2 interface consists of five pins on the T7264: the
data out (DO), data in (DI), data clock (C), K2 frame
sync (F), and master timing clock (MTC). C is a 512 kHz
output signal for clocking data into and out of the device
with 1 bit per clock cycle. F is an 8 kHz signal indicating
the beginning of a K2 frame. MTC is used in LT mode
and must be an 8 kHz
±
32 ppm system clock to meet
T1.601 requirements.
In LT mode, F is phase-locked to the MTC input through
the on-chip digital phase-locked loop. Jitter in MTC is
tracked by F at frequencies below 0.5 Hz. MTC jitter at
frequencies higher than 0.5 Hz is attenuated by the
phase-locked loop (PLL). In the NT mode, the F clock is
derived from incoming data from the U loop.
The first bit of a K2 frame begins simultaneously with
the rising edge of F. Transitions on DO occur following
the rising edge of C, and DI is latched on the falling
edge of C. Figure 8 shows the relationship between the
C, F, DO, and DI.
The K2 frame consists of eight octets for a total of
64 bits. These bits are transferred synchronously over
a 512 kHz interface with a frame rate of 8 kHz or 125
μ
s.
The major purpose of the K2 interface is to provide
2B+D data transfer between other devices and the chip.
In addition, there are framing bits (DF), U-interface
maintenance and control bits (UM), and device
control/status bits (DC/DS).
5-5167F
Figure 8. K2 Interface Timing
5-5158
Figure 9. K2 Octets
C
F
DO
DI
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
B1 TIME SLOT
C
F
DO
B1
B2
DF
UM1
UM3
DS
UM2
All 1s
DI
B1
B2
D
UM1
UM3
DC
UM2
All 1s
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