參數(shù)資料
型號: T7234
英文描述: Compliance with the New ETSI PSD Requirement
中文描述: 符合新的ETSI PSD的要求
文件頁數(shù): 80/116頁
文件大小: 1056K
代理商: T7234
Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
76
Lucent Technologies Inc.
Timing Characteristics
T
A
= –40
°
C to +85
°
C, V
DD
= 5 V
±
5%, GND = 0 V, crystal frequency = 15.36 MHz.
For Figure 28, assume register TDR0 = F9, DFR1 = 1E, and DFR0 = F5.
Table 40. TDM Bus Timing
* When connecting the T7256 TDM bus to Lucent devices with a CHI (concentration highway interface), the CHI must be able to withstand
45 ns of bus contention. For this length of time, two devices may be driving the bus. After this time, the output current is less than 10% of the
output high and output low currents. The TDMD0 pin on the T7256 was designed to withstand 80 ns of bus contention.
5-4682(C).a
Figure 28. TDM Bus Timing
Ref
1
2
3
4
5
6
7
8
9
10
Parameter
Min
162
195
25
25
Typ
8
2.048
230
260
Max
15
15
293
326
45*
50
Unit
kHz
ns
ns
MHz
ns
ns
ns
ns
ns
ns
FS Pulse Frequency
TDMCLK to FS High
TDMCLK to FS Low
TDMCLK Frequency
TDMCLK Width High
TDMCLK Width Low
Receive (TDMDI) Setup Time
Receive (TDMDI) Hold Time
Transmit (TDMDO) Time to High Impedance
TDMCLK to Transmit (TDMDO) Valid
1
B11
B12
B13
B14
B15
B28
D1
D2
B11
B12
1
2
3
4
5
16
17
18
1
2
B11
B12
B13
B14
B15
B28
D1
D2
B11
B12
4
6
5
8
7
2
10
3
FS
TDMCLK
TDMDO
TDMDI
9
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