參數(shù)資料
型號(hào)： T7234
英文描述： Compliance with the New ETSI PSD Requirement
中文描述： 符合新的ETSI PSD的要求
文件頁數(shù)： 111/116頁
文件大?。?/td> 1056K
代理商： T7234
Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
107
Glossary
(continued)
OUSCM:
Other U-interface state change
mask (register UIR1, bit 3).
PS1:
Power status #1 (register GR1,
bit 2).
PS1E/TDMDO:
Power status #1, TDM clock.
PS2:
Power status #2 (register GR1,
bit 1).
PS2E/TDMCLK:
Power status #2, TDM data out.
QMINT:
Quiet mode interrupt (register
MIR0, bit 0).
QMINTM:
Quiet mode interrupt mask
(register MIR1, bit 0).
QSC:
Q-bits state change (register
SIR0, bit 1).
QSCM:
Q-bits state change mask
(register SIR1, bit 1).
Q[4:1]:
Q-channel bits (register MCR0,
bits 0—3).
R25R:
Receive reserved bits
(register CFR2, bit 2).
R25T:
Transmit reserved bit
(register CFR0, bit 4).
R64T:
Transmit reserved bit
(register CFR0, bit 5).
RESET:
Reset.
RNR:
Receive negative rail for
S/T-interface.
RPR:
Receive positive rail for
S/T-interface.
RSFINT:
Receive superframe interrupt
(register UIR0, bit 4).
RSFINTM:
Receive superframe interrupt
mask (register UIR1, bit 4).
R[16:15]R:
Receive reserved bits
(register CFR2, bits 1—0).
R[16:15]T:
Transmit reserved bits
(register CFR0, bits 3—2).
R[64:54:44:34]R:
Receive reserved bits
(register CFR2, bits 6—3).
SAI[1:0]:
S/T-interface activity indicator
control (register GR1, bits 6—7).
SC1[4:1]:
S subchannel 1 (register MCR1,
bits 0—3).
SC2[4:1]:
S subchannel 2 (register MCR2,
bits 0—3).
SC3[4:1]:
S subchannel 3 (register MCR3,
bits 0—3).
SC4[4:1]:
S subchannel 4 (register MCR4,
bits 0—3).
SC5[4:1]:
S subchannel 5 (register MCR5,
bits 0—3).
SCK:
Serial interface clock.
SDI:
Serial interface data input.
SDINN:
Sigma-delta A/D negative input
for U-interface.
SDINP:
Sigma-delta A/D positive input for
U-interface.
SDO:
Serial interface data output.
SFECV:
S-channel far-end code violation
(register SIR0, bit 2).
SFECVM:
S-subchannel far-end code viola-
tion mask (register SIR1, bit 2).
SINT:
S/T-transceiver interrupt
(register GIR0, bit 1).
SIR0:
S/T-interface interrupt register.
SIR1:
S/T-interface interrupt mask
register.
SOM:
Start of multiframe (register SIR0,
bit 0).
SOMM:
Start of multiframe mask
(register SIR1, bit 0).
SPWRUD:
S/T-interface powerdown control
(register GR2, bit 1).
SRESET:
S/T-interface reset (register GR2,
bit 2).
STLED:
Status LED driver.
STOA:
S/T-only activation (register GR2,
bit 7).
Superframe:
Eight U-frames grouped together.
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