- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄383875 > T7234 Compliance with the New ETSI PSD Requirement PDF資料下載
參數(shù)資料
| 型號(hào)： | T7234 |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁(yè)數(shù)： | 72/116頁(yè) |
| 文件大?。?/td> | 1056K |
| 代理商： | T7234 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)當(dāng)前第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)
Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
68
Lucent Technologies Inc.
Application Briefs
(continued)
Interfacing the T7256 to the Motorola
68302
(continued)
To enable the TDMCLK and FS signals and generate
the FS signal in the proper time slot, the following
T7256 register bits must be programmed:
Register GR2, bit 5 (TDMEN) = 0.
Register DFR1, bits 7:5 (TDMDU, TDMB2U, TDMB1U)
= 000.
Register TDR0, bit 3:0 (FSP, FSC[2:0]) = 1111
(default).
Detailed information on T7256 activation control and
configuration of the microprocessor registers can be
found in the Application Briefs, Using the T7256 in a
Combination NT1/TA Environment section in this docu-
ment.
As an example of programming the MC68302 SIMODE
register bits for PCM mode, the following settings will
enable PCM mode and route the B2 channel to SCC1,
the B1 channel to SCC2, and the D channel to SCC3.
The ISDN signaling protocol stack (Q.931 and LAPD)
would communicate via SCC3, and any higher-layer
data protocol such as V.120 or V.110 would communi-
cate via SCC1 and SCC2, as required.
SETZ = 0, SYNC = 1, SDIAG1:SDIAG0 = 00, SDC2 =
0, SDC1 = 0, B2RB:B2RA = 01, B1RB:B1RA = 10,
DRB:DRA = 11, MSC3 = 0, MSC2 = 0, and MS1:MS0 =
01.
T7256 Serial Microprocessor Interface Support
The MC68302 SCP interface is a 3-wire serial interface
that may be directly connected to the T7256 micropro-
cessor interface. The SCP interface is implemented in
the MC68302 hardware, and the only software interac-
tion required is to set up the SCP interface, to transmit/
receive SCP bytes, and to respond to SCP events (the
SCP interrupt).
There are several points to note when interfacing the
T7256 to the MC68302 microprocessor interface.
1. Register bit CI (clock invert) in the MC68302
SPMODE register should be set to 1 to invert the
MC68302 SCP clock in order to meet the T7256
microprocessor timing specifications.
2. The MC68302 SCP clock, SPCLK, may be pro-
grammed to run as high as 4.096 MHz. The mini-
mum rate of the SCP SPCLK, assuming the slower
16.384 MHz version of the MC68302 with a maxi-
mum divide-down prescale of 64, is 256 kHz. The
minimum and maximum rates of the T7256 SCK are
60 kHz and 960 kHz, respectively, and care should
be taken to ensure that the MC68302 is pro-
grammed to a clock rate that is compatible with
T7256.
3. Every T7256 access consists of two 8-bit transfers,
where the first is the command/address byte and
the second is the data byte. There must be a delay
of 10
μ
s between every 8-bit register access to
meet the T7256 microprocessor timing specifica-
tions. The back-to-back byte transmit delay of the
MC68302 SCP at the slowest SPCLK rate of
256 kHz can be anywhere from two to eight clocks,
or 7.8
μ
s to 31.25
μ
s. To ensure that the 10
μ
s delay
requirement is met, the MC68302 software must not
send the second byte of the 2-byte sequence for at
least 10
μ
s after the SCP processor clears the
DONE bit in the SCP transmit/receive buffer
descriptor (refer to Section 4.6.2 of the Motorola
MC68302 User Manual for further information).
4. During 2-byte data transfer over the MC68302 SCP,
8 bits will be shifted into the SCP receive buffer for
every 8 bits shifted out. For a T7256 read, the first
byte in the receive buffer should be discarded and
the second byte will contain the read data from the
T7256. For a write, both bytes should be discarded
from the SCP receive buffer.
5. The T7256 microprocessor interface lacks an
enable pin to permit multiple device communication
on a single MC68302 SCP. In these applications,
the T7256 microprocessor interface can be enabled/
disabled using a microprocessor parallel port pin to
control a 3-state buffer at SCK (pin 15).
An alternative method of interfacing the MC68302 to
the T7256 microprocessor interface is to use three
MC68302 parallel port pins (e.g., PB0, PB1, and PB2
in Figure 23) programmed as outputs and supporting
the T7256 microprocessor interface in software. The
timing of the SCK, SDI, and SDO signals can be imple-
mented in software with a minimum amount of code.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T7234A | Compliance with the New ETSI PSD Requirement |
| T7237A | Compliance with the New ETSI PSD Requirement |
| T7256A | Compliance with the New ETSI PSD Requirement |
| T7288 | CEPT/E1 Line Interface(CEPT/E1 線接口) |
| T7290A | DS1/T1/CEPT/E1 Line Interface(DS1/T1/CEPT/E1 線接口) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T7234A | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:Compliance with the New ETSI PSD Requirement |
| T7237 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Compliance with the New ETSI PSD Requirement |
| T7237A | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:Compliance with the New ETSI PSD Requirement |
| T7240 | 制造商:TE Connectivity 功能描述: |
| T7-241A5 | 功能描述:撥動(dòng)開(kāi)關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開(kāi)關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類(lèi)型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。