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SCSI Functional Description
2-45
edge. Setting this bit reduces the synchronous transfer send rate but will
not reduce the rate at which the SYM53C1010 receives outbound REQs,
ACKs, or data.
Bit 0, XCLKS_ST (Extra Clock of Data Setup on ST transfer edge), adds
a clock of data setup to synchronous DT or ST SCSI transfers on the ST
edge. This bit impacts DT and ST transfers as it affects data hold to the
ST edge. Setting this bit reduces the synchronous transfer send rate but
will not reduce the rate at which the SYM53C1010 receives outbound
REQs, ACKs, or data.
The synchronous receive rate can be calculated using the following
formula:
Note:
The receive rate is independent of the settings of the
XCLKS_DT, XCLKS_ST, XCLKH_DT, XCLKH_ST bits.
The synchronous send rate, in units of megatransfers/s, can be
calculated using the following formula:
To configure the SYM53C1010 for Ultra3 DT transfers, perform the
following steps:
Step 1.
Enable the SCSI Clock Quadrupler – The SYM53C1010 can
quadruple the frequency of a 40 MHz SCSI clock, allowing the
system to perform Ultra3 SCSI transfers. This option is user
selectable through bit settings in the
SCSI Test One (STEST1)
register. At power-up or reset, the quadrupler is disabled and
powered down. Follow the steps in the bit description to enable
the clock quadrupler.
Receive Rate (DT)
)
---------------------------------------------
(megatransfers/s)
=
Receive Rate (ST)
)
---------------------------------------------
(megatransfers/s)
=
Send Rate (DT)
SCF Divisor
2
--------------------------------------------------------------------------------------------------------------------------------------
+
×
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=
Send Rate (ST)
+
(
SCF Divisor
)
×
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=