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Index
IX-7
space
2-3
,
2-4
to memory
2-19
to memory moves
2-19
write
2-12
,
2-13
write and invalidate
2-11
write and invalidate command
2-9
write caching
2-13
write command
2-6
write enable
3-23
Min_Gnt (MG[7:0])
4-17
MOE/_TESTOUT
3-23
,
3-24
move to/from SFBR cycles
5-25
multiple cache line transfers
2-9
MWE/
3-23
N
new capabilities (NC)
4-6
new features in the SYM53C1010
1-4
next item pointer register
4-18
Next_Item_Ptr (NIP[7:0])
4-18
no download mode
2-63
no flush
5-35
store instruction only
5-39
nonburst opcode fetch
32-bit address and data
6-22
normal/fast memory ( 128 Kbytes)
multiple byte access read cycle
6-48
multiple byte access write cycle
6-50
single byte access read cycle
6-44
single byte access write cycle
6-46
O
opcode
5-10
,
5-15
,
5-23
,
5-27
fetch burst capability
2-33
operating conditions
6-2
operating register/SCRIPTS RAM read
32-bit
6-17
64-bit
6-18
operating register/SCRIPTS RAM write
32-bit
6-19
64-bit
6-20
operator
5-23
output
current as a function of output voltage
6-10
output signals
6-5
P
PAR
3-10
PAR64
3-11
parallel ROM interface
2-60
parallel ROM support
2-61
parity
3-10
error
3-13
(PAR)
4-77
options
2-34
parity64
3-11
PCI
addressing
2-3
bus commands and encoding types
2-5
bus commands and functions supported
2-4
cache line size register
2-9
cache mode
2-11
command register
2-9
commands
2-4
configuration info enable (PCICIE)
4-54
configuration register read
6-15
configuration register write
6-16
configuration registers
4-1
configuration space
2-3
external memory interface timing diagrams
6-13
functional description
2-2
I/O space
2-3
interface signals
3-9
master transaction
2-12
master transfer
2-11
memory space
2-4
performance
1-9
target disconnect
2-10
target retry
2-10
PERR/
3-13
phase mismatch
handling in SCRIPTS
2-20
jump address one (PMJAD1)
4-112
jump address two (PMJAD2)
4-113
physical longword address and data
3-10
PME
clock (PMEC)
4-19
enable (PEN)
4-20
status (PST)
4-20
support (PMES)
4-18
polling
2-47
power
and ground signals
3-25
management
2-63
capabilities
4-18
control/status
4-20
state (PWS[1:0])
4-20
state D0
2-64
state D1
2-64
state D2
2-65
state D3
2-65
prefetch
enable (PFEN)
4-68
flush
2-33
flush (PFF)
4-68
SCRIPTS instructions
2-32
pull-ups, internal, conditions
3-8
R
RAM, see also SCRIPTS RAM
2-20
RBIAS
3-25
read
line
2-11
,
2-12
line function
2-8
modify-write cycles
5-24
multiple
2-8
,
2-11
,
2-12
multiple with read line enabled
2-8
write instructions
5-23
write system memory from a SCRIPT
5-35
read/write
instructions
5-23
,
5-25
system memory from a SCRIPT
5-35
received
master abort (from master) (RMA)
4-5
target abort (from master) (RTA)
4-5
register
address
5-39