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3-6
Signal Descriptions
Table 3.3
Signal
Name
Signal Names and BGA Position
Signal
BGA
Name
Pos
A_DIFFSENS
A_GPIO0_
FETCH/
A_GPIO1_
MASTER/
A_GPIO2
A_GPIO3
A_GPIO4
A_SACK
A_SACK+
A_SATN
A_SATN+
A_SBSY
A_SBSY+
A_SC_D
A_SC_D+
A_SD0
A_SD0+
A_SD1
A_SD1+
A_SD2
A_SD2+
A_SD3
A_SD3+
A_SD4
A_SD4+
A_SD5
A_SD5+
A_SD6
A_SD6+
A_SD7
A_SD7+
A_SD8
A_SD8+
A_SD9
A_SD9+
A_SD10
A_SD10+
A_SD11
A_SD11+
A_SD12
A_SD12+
A_SD13
A_SD13+
A_SD14
A_SD14+
A_SD15
A_SD15+
A_SDP0
A_SDP0+
A_SDP1
A_SDP1+
A_SI_O
A_SI_O+
A_SMSG
A_SMSG+
A_SREQ
A_SREQ+
A_SRST
A_SRST+
A_SSEL
A_SSEL+
ACK64/
AD0
AD1
AD2
AD3
A20
AB16
Y16
AA16
AC17
AB17
C13
A14
B11
B12
C12
A12
C15
A16
B6
A6
C7
B7
A7
C8
D8
B8
A8
C9
D9
B9
A9
C10
D11
B10
A18
B18
D18
C18
A19
B19
D19
C19
C4
A3
B4
A4
C5
D5
B5
A5
A10
C11
C6
D6
B17
C17
C14
A15
C16
A17
B14
D13
B15
D15
AB1
Y3
AA1
Y2
Y1
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AD39
AD40
AD41
AD42
AD43
AD44
AD45
AD46
AD47
AD48
AD49
AD50
AD51
AD52
AD53
AD54
AD55
AD56
AD57
AD58
AD59
AD60
AD61
AD62
AD63
ALT_INTA/
ALT_INTB/
B_DIFFSENS
B_GPIO0_
FETCH/
B_GPIO1_
MASTER/
W3
W4
W2
W1
V4
V2
V1
U3
U2
U1
T3
T4
N3
N1
N2
M2
M3
M1
L2
L1
K2
L4
K3
J1
J2
J4
J3
H1
AC14
AA13
AC13
AB13
AB12
AA12
AC12
AB11
AC11
AA11
AC10
AB10
Y11
AA10
AC9
AB9
Y9
AA9
AC8
AB8
Y8
AA8
AC7
AB7
AA7
AC6
AB6
Y6
AA6
AC5
AB5
Y5
F1
G3
Y21
AA14
AC15
B_GPIO2
B_GPIO3
B_GPIO4
B_SACK
B_SACK+
B_SATN
B_SATN+
B_SBSY
B_SBSY+
B_SC_D
B_SC_D+
B_SD0
B_SD0+
B_SD1
B_SD1+
B_SD2
B_SD2+
B_SD3
B_SD3+
B_SD4
B_SD4+
B_SD5
B_SD5+
B_SD6
B_SD6+
B_SD7
B_SD7+
B_SD8
B_SD8+
B_SD9
B_SD9+
B_SD10
B_SD10+
B_SD11
B_SD11+
B_SD12
B_SD12+
B_SD13
B_SD13+
B_SD14
B_SD14+
B_SD15
B_SD15+
B_SDP0
B_SDP0+
B_SDP1
B_SDP1+
B_SI_O
B_SI_O+
B_SMSG
B_SMSG+
B_SREQ
B_SREQ+
B_SRST
B_SRST+
B_SSEL
B_SSEL+
C_BE0/
C_BE1/
C_BE2/
C_BE3/
C_BE4/
C_BE5/
C_BE6/
C_BE7/
CLK
DEVSEL/
AB15
AA15
AC16
N20
P21
M23
N22
N23
N21
T20
T21
G21
G22
G23
H21
H20
H22
H23
J21
J20
J22
J23
K21
L20
K22
K23
L21
V21
W23
W22
W20
W21
Y23
Y22
AA23
D22
D23
E21
E20
E22
E23
F21
F20
L23
L22
F22
F23
V22
V20
R20
R21
U21
V23
R23
R22
T23
T22
V3
T2
P1
K1
AC4
AB4
AC3
AA4
H3
R1
FRAME/
GNT/
IDSEL
INT_DIR
INTA/
INTB/
IRDY/
MAD0
MAD1
MAD2
MAD3
MAD4
MAD5
MAD6
MAD7
MAS0/
MAS1/
MCE/
MOE/_TESTOUT
MWE/
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PAR
PAR64
PERR/
RBIAS
REQ/
REQ64/
RESERVED
RST/
SCAN_MODE
SCLK
SERR/
STOP/
TCK
TDI
TDO
TEST_HSC
TMS
TRDY/
TEST_PD
TEST_RST/
V
DD
_IO
V
DD
_IO
V
DD
_IO
V
DD
_IO
V
DD
_IO
V
DD
_IO
V
DD
_IO
V
DD
_IO
V
DD
_IO
V
DD
_IO
V
DD
_IO
V
DD
_IO
V
DD
_IO
P2
H4
L3
G2
F4
F2
N4
AC23
AB21
AC22
AA20
AB20
AC20
AA19
Y19
AC18
AA17
AA18
Y18
AC19
A1
A13
A23
B1
B3
B13
B16
B21
D16
U22
U23
P22
P23
AB22
T1
AA5
R4
M21
H2
AA2
AB14
G1
C22
A21
R3
R2
D1
E2
E1
C23
E3
P3
A2
C1
D7
D10
D14
D17
G4
K4
K20
P4
P20
U4
U20
Y7
Y10
V
DD
_IO
V
DD
_IO
V
DD
_A
V
DD
_A
V
DD
_BIAS
V
DD
_BIAS2
V
DD
_CORE
V
DD
_CORE
V
DD
_CORE
V
DD
_CORE
V
DD
_CORE
V
DD
_CORE
V
DD
_CORE
V
DD
_CORE
V
DD
_CORE
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_IO
V
SS
_A
V
SS
_A
V
SS
_CORE
V
SS
_CORE
V
SS
_CORE
V
SS
_CORE
V
SS
_CORE
V
SS
_CORE
V
SS
_CORE
V
SS
_CORE
V
SS
_CORE
V
SS
_CORE
Y14
Y17
B2
C20
M22
A11
B22
B23
D3
E4
Y13
AB3
AB18
AB23
AC1
C3
C21
D4
D12
D20
K10
K11
K12
K13
K14
L10
L11
L12
L13
L14
M4
M10
M11
M12
M13
M14
M20
N10
N11
N12
N13
N14
P10
P11
P12
P13
P14
Y4
Y12
Y20
AA3
AA21
B20
C2
A22
D2
D21
F3
Y15
AB2
AA22
AB19
AC2
AC21
Signal
Name
BGA
Pos
Signal
Name
BGA
Pos
Signal
Name
BGA
Pos
Pos
BGA