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參數(shù)資料
| 型號： | STLC7549 |
| 廠商： | 意法半導體 |
| 元件分類： | Codec |
| 英文描述： | Stereo Audio/MODEM/Telephony Codec(立體聲音頻/調(diào)制解調(diào)器/電話編解碼器) |
| 中文描述： | 立體聲音頻/調(diào)制解調(diào)器/語音編解碼器（立體聲音頻/調(diào)制解調(diào)器/電話編解碼器） |
| 文件頁數(shù)： | 8/35頁 |
| 文件大?。?/td> | 335K |
| 代理商： | STLC7549 |
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Pin N
°
Symbol
Type
Function
HOST INTERFACE (25 pins) (continued)
Serial Interface #2 Dedicated for Modem and Telephony Codecs.
The serial modem interface is synchronous with the modem sampling frequency (FSM).
54
SIN2
I
Data Input. Digital modem and telephony data to the DACs are received by the
STLC7549 via SIN2.
53
SOUT2
O
Data Output. Digitalmodem and telephony data from the ADCs are output from the
STLC7549 via SOUT2.
52
SCLK2
O
Serial Port #2 Bit Clock Output. Clocks the digital data into SIN2 and out of SOUT2
during the frame synchronization interval. The Serial bit clock isgenerated internally
and equal to the Master clock signal frequency MCLKM/4. In quadraphonic mode
SCLK2 is equal to MCLKA/4 (refer to Figure 6).
51
FSYNC2
O
Serial Port #2 Frame Synchronization Output. The frame synchronization signal is
used to indicate that the device is ready to send and receive data. The data transfer
begins on the falling edge of the frame-sync signal. The frame-sync is generated
internally and goes low on the rising edge of SCLK2. FSYNC2 and FSM have the
same frequency.
50
MCLKM
I
Master Clock M for Modem and Telephony Codecs. Master clock input for modem
codecs. In quadraphonic mode this input is ignored. This signal is the oversampling
clock of the DA and AD convertor. It also provides all the clocks of the modem serial
interface #2. This input may be driven by a signal with a frequency from 1.8432MHz
to 3.84MHz (up to 11.2896MHz in Quadraphonic mode).
Miscellaneous
64
RESET
I
Reset Function (active low). A reset function to initalize the internal counters and
controlregister.A minimum low pulse of100ns is requiredto reset thechip.This reset
function initiates the serial data communications. The reset function will initialize all
the registers to their default value and will put the device in a pre-programmed state.
Master clocks arenot necessary during RESET .
63
PDWN
I
Power Down (active low). The Power-Down input powers down the entire chip to
0.5mW. When PDWN pin is taken low, the device is powered down such that the
existing internally programmed state is maintainedand all analog outputsare in high
impedance. When PDWN is driven high, full operation resumes. If the PDWN input
is not used, it should be tied to V
DD
.
Test Input. Digital input reserved for test. Should be connected to GND.
62
TEST
I
38
VOL_UP
I
Pushbutton Lineout Control Volume UP (edge sensitive, active low, internal pull-up).
This pin increases the volume and also affects the leftand rightgain select valuesin
register 10.
39
VOL_DOWN
I
Pushbutton Lineout Control Volume DOWN (edge sensitive, active low, internal
pull-up). This pin decreases thevolume and also affects the left and right gainselect
values in the register 10.
37
VOL_MUTE
I
Pushbuttons Lineout Control Volume MUTE (edge sensitive, active low, internal
pull-up).Thispin mutes and unmutes (toggle function) the Left andRight attenuators
overriding the mute bits in registers 11 and 12 (refer to Figure 10).
36
DC_POT
I
DC Potentiometer Control Lineout Volume. An external potentiometer can be
attachedto this pinto determine a 4-bitvalue tobe used asthe mainLeft/Rightoutput
attenuator register value (register10).
49 : 42
GPIO[0:7]
I/O
General Purpose I/Os.General purpose input/output pins*.
These I/Os areconfigured as inputs at power-up orRESET.
* Each bit can be configured as input or output(Register 18), set and read via Serial Interface #1 (see Figure 23).
7
PIN DESCRIPTION
(continued)
STLC7549
8/35
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| STLC7550 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW POWER LOW VOLTAGE ANALOG FRONT END |
| STLC7550TQF7 | 功能描述:電信線路管理 IC Lo-V Analg Front-End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| STLC7550TQF7TR | 功能描述:電信線路管理 IC Lo-V Analg Front-End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| STLC7550TQFP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW POWER LOW VOLTAGE ANALOG FRONT END |
| STLC75C53TQFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MODEM |
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