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參數(shù)資料
| 型號： | STLC7549 |
| 廠商： | 意法半導體 |
| 元件分類： | Codec |
| 英文描述： | Stereo Audio/MODEM/Telephony Codec(立體聲音頻/調制解調器/電話編解碼器) |
| 中文描述： | 立體聲音頻/調制解調器/語音編解碼器（立體聲音頻/調制解調器/電話編解碼器） |
| 文件頁數(shù)： | 16/35頁 |
| 文件大?。?/td> | 335K |
| 代理商： | STLC7549 |
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FUNCTIONAL DESCRIPTION
(continued)
9 - Reset
The reset function initializes the internal counters
and control registers. A minimum low pulse of
100nsis requiredto reset the chip.
Thisreset functioninitiatesthe serialdata commu-
nication.
During a reset:
- analog outputs takerespective VCMx values
- SCLK1 and SCLK2 arehigh,
- FSYNC1 and FSYNC2 are low,
- SOUT1 and SOUT2are in ”X” state,
- reference voltages VREFxx and VCMx are not
affected.
Aftera reset,
- registersare set to default values :
- all muteblocksare settomuteexceptMono_In
to Mono_Outpath in orderto allow PC beepto
be heardduring configuration,
- theoutputof TOGGLE/UNTOGGLEmutefunc-
tion is placed in unmutestate,
- gain and attenuation blocks takes the values
shown in Table1.,
- sample frequency ratio NDIV (register 20)
takes the value 1 (with a master clock fre-
quency of 11.2896MHz), sample frequency is
44.1kHz),
- no loopbackbetweenADC and DAC channels,
- GPIO[7:0]are set to input configuration
- no quadraphonic mode, Modem and Teleph-
ony part use MCLKM clock input without N
divider,
- no blocksin powerdownmode.
- the calibrationsof all convertersare low,
- all the internaldata pathsare set to ”0” (seeFig-
ure 16).
At power-up sequence, a reset is required by the
DSP or with a RC network on the NRESET
DSP Pin.
Table 1
Defaut Values
Reg.
Gain/
Attenuation
-24dB
-24dB
-24dB
0dB
0dB
0dB
0dB
0dB
-10dB
0dB
0dB
-4dB
0dB
Line inputs #1 gain
Line inputs #2 gain
Line inputs #3 gain
Right microphone input gain
Right microphone pre-amp gain
Left microphone input gain
Left microphone pre-amp gain
Audio line outputattenuation
Mono input gain
Modem Codec #1 input gain
Modem Codec #1output attenuation
Modem Codec #2 input gain
Modem Codec #2output attenuation
1
2
3
4
4
5
5
10
12
13
14
15
16
10 - Powerdown
The PDWN input powers down the entire chip.
Minimumpowerconsumptionis obtainedwhenthe
MCLKxclocks are stopped.
WhenPWDN Pin is takenlow,
- the exiting programmed state is maintained,
- datapathandclockgenerationarereset(seeFig-
ure 16),
- analog outputs are in high impedance state
(MONO_OUT included),
- SCLK1and SCLK2 are high,
- FSYNC1and FSYNC2are low,
- SCOUT1 and SCOUT2 are in ”x” state,
- V
CMx
Pin takes their respective supply values
(V
CMA
≥
AV
VDA
and V
CMM
≥
AV
DDM
) through an
approximatively1k
resistor,
- V
REFx
Pin follows respective V
CMx
values, i.e.
respectivesupplyvaluesthroughapproximatively
10k
resistor (V
REFPA
and V
REFFNA
≥
AV
DDA
,
V
REFPM
andV
REFNM
≥
AV
DDM
).
In order to limit eventual noises, it is adviced to
resetthe chipduringexitingpowerdownmodeuntil
the chipis completelywake up. Timesfor entering
or exiting powerdown mode depends of capacity
values C placed on voltage references Pins V
CMx
and V
REFx
.
T = K . C with K = 30.000sec/F
With recommended value C = 10
μ
F (see Fig-
ure 14), T#300ms. When not used,this pin should
be tied to DV
DD
.
The STLC7549 provides also 3 software modes
detailedin register 20.
RESET
Reset Data
Path andClock
Generation
Reset Hard
(Register)
PWRDWN
PowerDown
Analog Part
7
Figure 16
STLC7549
16/35
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| STLC7550 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW POWER LOW VOLTAGE ANALOG FRONT END |
| STLC7550TQF7 | 功能描述:電信線路管理 IC Lo-V Analg Front-End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| STLC7550TQF7TR | 功能描述:電信線路管理 IC Lo-V Analg Front-End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| STLC7550TQFP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW POWER LOW VOLTAGE ANALOG FRONT END |
| STLC75C53TQFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MODEM |
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