
3 - Input Gain and Output Gain Setting
Both input and output gain setting are internally
made on zero crossing of the analog signal to
minimize the ” zipper ” noise. The gain setting on
zero crossing of the analog signal is not available
in the preamplifier P. The gain change automat-
ically takes effect if zero crossing does not occur
within 512 frames. The 512 frames counter is in-
itializedby the registergain access.
4 - A/D and D/AConverters
4.1 - OffsetCancellation
Theinternal inputoffsetsare minimized byinternal
offsetcancellationcircuitry. The calibration proce-
dureis forcedbysettingbit0 orbit1 of Register19
to ”1”. The lengh of time required for calibrationis
1024 samples at the sampling frequency rate
(eg: FSx = 44.1kHz, T = 1024 * 1/FSx = 23ms).
When calibration is completed the bit 0 or bit 1 of
Register 19 is reset to ”0”. During calibration the
analog inputs are set to a high impedance state,
outputpathare reset, and the data valueat SOUT
arenot valid.
Calibration of all converters are lost during reset
operation, and no calibration is done after Reset
and Powerdown.
ADCoffsetisprincipalydependingof chiptempera-
ture.Itis advisedto waita whileat power-upbefore
proceedingto a calibration sequence,to allow the
chiptotake its typicaltemperature.Calibrationcan
also be made in case of saturation to minimize
distortion.
4.2 - Converter Saturation
ADCandDACconversionfullrangeis 1V
RMS
.Each
analog-to-digitalconverter is featured by an over-
flow flag. These flags are reflectedin serial output
#1 (bits 16, 17, 18 and 19) and can be cleared by
setting bit 0,1,2 and 3 in register 21.
When several lines are mixed, signals should be
attenuatedbefore mixing in order to provideto the
A/D converter a resulting summed signal within
1V
RMS
.
5 - QuadraphonicMode
The STLC7549 offers the possibility to play music
in quadraphonicmode.Thismode will allow you to
power your multimedia application by providing
surroundsoundusing RQ1(RightQuadraphonic1
output) and LQ1 (Left Quadraphonic 1 output)
along with the normal stereo outputs Lout1 and
Rout1.
FUNCTIONAL DESCRIPTION
(continued)
This mode is programmedby setting the bit MAM
(ModemAudioMode,Register20)andthebitMOR
(Modem Oversampling Ratio, register 20) to ”1”.
Thiswillcausethemodemcodecs#1and#2clocks
to be controlled from the audio master clock
MCLKA (11.2896MHz ) and to have the same
oversamplingratiothantheaudiopart.Themodem
master clockMCLKM will be ignored(see CLOCK
GENERATORDIAGRAM)(Figure 6) and synchro-
nization signals FSYNC1 and FSYNC2 will in
phase.
In this mode the FSA
to 44.1kHz (NDIV1 and NDIV0 of Register 20
equals zero so N=1). FSM will be equal to
MCLKA/4/64= 44.1kHz.
must be programmed
6 - AnalogInputs and Outputs
6.1- AudioAnalog Input
The audio analog input full scale is 1V
RMS
. Note
that compact dics player output levels is 2V
RMS
centeredaround analog ground. To preventeven-
tualdistortion,signalcomingfromCDplayershould
be externalyattenuatedby a resistivedivider.
All analog inputs must have an external capaci-
tanceas shownon Figure11.
6.2- AnalogAudioOutputs
Analogaudiooutputfullscaleis1V
RMS
centeredat
V
CMA
, and the minimum load must be 10k
. An
externalsingle pole smoothing filteris advicedfor
large bandpass speakers. Suggested filter is
shown on Figure 11.
STLC7549integrates sinx/x error correctorfilters.
1
μ
F
1
μ
F
10k
100pF
AGND
Line Output
Line Input
STLC7549
7
Figure 11
6.3 - Modem Interface
Suggested duplexors for Modem interface are
shown on Figures 12 and 13.
STLC7549
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