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參數(shù)資料
| 型號(hào)： | STLC7549 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | Codec |
| 英文描述： | Stereo Audio/MODEM/Telephony Codec(立體聲音頻/調(diào)制解調(diào)器/電話編解碼器) |
| 中文描述： | 立體聲音頻/調(diào)制解調(diào)器/語音編解碼器（立體聲音頻/調(diào)制解調(diào)器/電話編解碼器） |
| 文件頁數(shù)： | 7/35頁 |
| 文件大小： | 335K |
| 代理商： | STLC7549 |
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Pin N
°
Symbol
Type
Function
MODEM AND TELEPHONY CODEC (13 pins) (continued)
29
TP1Tx+
O
Modem #1 Differential Positive Output. This pin is the noninverting output of the fully
differential transmit output modem #1.
Modem #1 Differential Negative Output. This pin is the inverting output of the fully differential
transmitoutputmodem#1.OutputsTP1Tx+andTP1Tx-provideanalogsignalswithmaximum
peak-to-peak amplitude 2 x V
, and must be followed by an external two pole smoothing
filter. The external filter follows the internal single pole switch capacitor filter with cut-off
frequencyof 2xFSM.Thecut-offfrequencyoftheexternalfiltermustbegreaterthantwotimes
the sampling frequency (FSM),so thatthe combined frequency response of both the internal
and external filters is flat in theband-pass.
Modem #1 Differential Positive Analog Input. This pin is the differential non-inverting ADC
input.
Modem #1 Differential Negative Analog Input. This pin is the differential inverting receive
input. The analog input peak-to-peak differential signal range must be less than 2 x V
,
and must be preceeded by an external single pole anti-aliasing filter. These filters should
be setas close as possible to the TP1Rx+ (TP1Rx-) pins.
Modem #1 Auxiliary Analog Output or left channel output in quadraphonic mode (LQ1).
This pin is the single-ended auxillary modem output. This output provides analog signals
with maximum peak-to-peak amplitude V
, and must be followed by an external two
pole smoothing filter.The externalfilterfollowsthe internalsinglepole switchcapacitorfilter.
The cut-off frequency of the external filter must be greater than two times the sampling
frequency (FSM),so thatthecombined frequencyresponse ofboththe internalandexternal
filters is flat in the band-pass.
TelephonySingle-ended Outputs or rightchannel outputin quadraphonic mode for TP2Tx
(RQ1). These pins are the single-ended outputs of the analog smoothing filter. With
maximum peak-to-peak amplitude V
, and must be followed by an external two pole
smoothing filter. The external filter follows the internal single pole switch capacitor filter.
The cut-off frequency of the external filter must be greater than two times the sampling
frequency (FSM),so thatthecombined frequencyresponse ofboththe internalandexternal
filters is flat in the band-pass.
Telephony Single-ended Input. These pins are the single-ended Telephony ADC input. The
analog input peak-to-peak single-ended signal range must be less than V
, and must be
preceeded by anexternalsingle pole anti-aliasing filter.Thesefilters should besetas closeas
possible tothe TP2Rx, HandRx pins.
30
TP1Tx-
O
27
TP1Rx+
I
28
TP1Rx-
I
31
TP1Tx2
(LQ1)
O
34
33
32
HandTx1,
HandTx2,
HandTx3
(TP2Tx)
(RQ1)
O
26
22
HandRx
TP2Rx
I
HOST INTERFACE (25 pins)
Serial Interface #1 Dedicated for Stereo Audio Codec.
The serial audiointerface is synchronous with the audio sampling frequency (FSA).
61
SIN1
I
Data In. Digitalaudio data to the DACs,control information, GPIO data are received by the
STLC7549 via SIN1. Refer to ”Serial Interface Bit Definition” on Page 26.
60
SOUT1
O
Data Out. Digitalaudio data from the ADCs, status information, GPIO data are output from
the STLC7549 via SOUT1. Refer to ”Serial Interface Bit Definition” on Page 26.
59
SCLK1
O
Serial Port #1 Bit Clock Output. Clocks the digitaldata intoSIN1 and out of SOUT1 during
the frame synchronization interval. The Serial bit clock is generated internally and is equal
to the audio Master clock signal frequency MCLKA/(4 x N) where N depends on index
register 20 contents.
58
FSYNC1
O
Serial Port #1 Frame Synchronization Output.The frame synchronization signalis used to
indicate thatthe device isready to send and receive data. The data transfer begins on the
falling edge of the frame-sync signal. The frame-sync is generated internally and goes low
on the rising edge of SCLK1. FSYNC1 and FSA have the same frequency.
55
MCLKA
I
Master Clock A for Audio Codec. Master clock input for audio codecs. This signal is the
oversampling clock of the DA and AD convertor. It also provides all the clocks of the audio
serial interface #1. This input must be driven by a signal with a frequency from 6.144MHz
to 12.288MHz. Inquadraphonic modethisinputprovideallCodecs clocksoftheSTLC7549.
7
PIN DESCRIPTION
(continued)
STLC7549
7/35
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STLC7550 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW POWER LOW VOLTAGE ANALOG FRONT END |
| STLC7550TQF7 | 功能描述:電信線路管理 IC Lo-V Analg Front-End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| STLC7550TQF7TR | 功能描述:電信線路管理 IC Lo-V Analg Front-End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| STLC7550TQFP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW POWER LOW VOLTAGE ANALOG FRONT END |
| STLC75C53TQFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MODEM |
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