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參數(shù)資料
| 型號(hào)： | STLC7549 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類(lèi)： | Codec |
| 英文描述： | Stereo Audio/MODEM/Telephony Codec(立體聲音頻/調(diào)制解調(diào)器/電話編解碼器) |
| 中文描述： | 立體聲音頻/調(diào)制解調(diào)器/語(yǔ)音編解碼器（立體聲音頻/調(diào)制解調(diào)器/電話編解碼器） |
| 文件頁(yè)數(shù)： | 15/35頁(yè) |
| 文件大?。?/td> | 335K |
| 代理商： | STLC7549 |
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7 - General Purpose Input/Output :
GPIO[7:0]
TheSTLC7549offers8generalpurposeInput/Out-
put pins.The setting of the GPIO configuration is
done through Register 18 (bit set to ”0” for input
configuration and bit set to ”1” for output configu-
ration).OnRESETthepinsareconfiguredas Input.
The GPIO value is reflected in the serial data
stream SOUT1 bits 24-31 (eg : could be used for
Ring detect in modem application). When pro-
grammed as output the GPIOprovides the way to
controlexternaldevicesusingbitsintheserialdata
inputstreamSIN1 bits56-63(eg: couldbe usedfor
controlling relay drivers) .The GPIO input voltage
isindependantofDV
DD
andcanbefrom3.3Vto 5V.
GPIarelatchedat thebeginningof the frameinput
word #1 (TSI11) and GPO are switching at the
middle of the frame output word #0 (TSO10) as
shownin Figure15.
Seealso Figures 14 and 22.
8 - Clock Generator
FromtheMasterClockAudio(MCLKA)andMaster
Clock Modem(MCLKM) the internal clock gen-
eratorprovidesall the synchronousserialinterface
clocks (SCLK1, FSYNC1, SCLK2and FSYNC2).
Theinternalsamplingfrequency(FSA, FSM)used
GPIO [7:0]
DGND
Output Enable
(Register 18)
Input
Output
(bits 56-63)
STLC7549
DV
DD
7
Figure 14
FUNCTIONAL DESCRIPTION
(continued)
for A/D and D/A conversion are equal to the syn-
chronous frequency (FSYNC1 and FSYNC2 re-
spectively). FSx andFSYNCxfrequenciesare not
in phase.
InQuadraphonicmodetheMCLKMinputis ignored
and the reference master clock is MCLKA. For
proper operationthe N divider (Register 20) must
be set to 1 in orderto have FSAand FSM equals.
The modem codecs can run with master clock
higherthan 3.84MHz (e.g. : 11.2896MHz)but with
reduced performances.
0
1
7
8
9
15
16
17
TSI10
TSI11
SCLK1
FSYNC1
SIN1
GPO
GPI
TSO10
TSO11
Index Data Register
Audio Left Data
7
Figure 15
STLC7549
15/35
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STLC7550 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:LOW POWER LOW VOLTAGE ANALOG FRONT END |
| STLC7550TQF7 | 功能描述:電信線路管理 IC Lo-V Analg Front-End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| STLC7550TQF7TR | 功能描述:電信線路管理 IC Lo-V Analg Front-End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| STLC7550TQFP | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:LOW POWER LOW VOLTAGE ANALOG FRONT END |
| STLC75C53TQFP | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MODEM |
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