參數(shù)資料
型號： STLC7549
廠商： 意法半導體
元件分類： Codec
英文描述： Stereo Audio/MODEM/Telephony Codec(立體聲音頻/調制解調器/電話編解碼器)
中文描述： 立體聲音頻/調制解調器/語音編解碼器（立體聲音頻/調制解調器/電話編解碼器）
文件頁數(shù)： 34/35頁
文件大小： 335K
代理商： STLC7549
REGISTERDESCRIPTION
(continued)
Index Register20 :
DigitalControl Register #2
7
6
5
4
3
2
1
0
0
0
M
M
N
N
S
S
MOR : Resetvalue: 0. Whenthisbitis set to1 themonocodecs#1 and#2 havethe sameratiothanaudio
part,(N value,register20). When set to 0, monocodecshave an oversamplingratiofixed to 128.
MAM : Reset value :0. Mono codecs #1 and #2 clocks derived from MCLKM when set to 0. If this bit is
set to 1, all codecsclocks are issuedfrom MCLKA(quadraphonicmode) (see Figure6).
MOR MAM
0
0
1
1
SCLK1
MCLKA/(4
N)
MCLKA/(4
N)
MCLKA/(4
N)
MCLKA/(4
N)
FSA
SCLK2
MCLKM/4
MCLKA/4
MCLKM/(4
N)
MCLKA/(4
N)
FSM
Modem mode
Common master clock
Common ratio
Quadraphony
Seealso Figure 6 forclock generator diagram.
NDIV1, NDIV0
: Reset value : 00. Ratio FSAversusMCLKA: see Table11.
Typical sampling frequencyobtainedwithMCLK = 11.2896MHz: see Table12.
SWPDN1, SWPDN0 : Reset value : 00. Softwarepower-downmode options(seeTable 13).
0
1
0
1
MCLKA/(256
N)
MCLKA/(256
N)
MCLKA/(256
N)
MCLKA/(256
N)
MCLKM/256
MCLKA/256
MCLKM/(256
N)
MCLKA/(256
N)
Table 11:
SamplingFrequency Setting
Bit 3
0
0
1
1
Bit 2
0
1
0
1
N
1
2
4
8
FSA
24kHz
→
48kHz
12kHz
→
24kHz
6kHz
→
12kHz
3kHz
→
6kHz
Table 12 :
Typical FSAwith MCLKA=11.2896MHz
Bit 3
Bit 2
0
0
0
1
1
0
1
1
N
1
2
4
8
FSA
44.1kHz
22.05kHz
11.025kHz
5.5125kHz
Table 13
Bit 1 Bit 0
0
0
Power-down Mode
0
1
SWPDNMode 0 : allcodec circuitry isactive.
SWPDN Mode 1 : Audio left/right ADC/DAC are powered down. Mono codecs #1 and #2 areactive. All input
and output analog mixers, GPIO and pushbuttons are active. Serial port #1 active. Serial port #2 active.
SWPDN Mode 2 : Audio left/rightADC/DAC are active. Monocodecs #1 and #2 are powered down. All input
and output analog mixers, GPIO and pushbuttons are active. Serial port #1 active. Serial port #2 in-active.
1
0
Index Register21 :
SaturationClear Register
7
6
5
4
3
2
1
0
0
0
0
0
A
A
A
A
ADC LEFT,ADC RIGHT, ADC MODEM #1, ADC MODEM#2
Whenbitis setto 1,theSTLC7549will clearthe respectiveADC overflowbitintheserialoutput datastream
periods.This is a write only register.
: Reset value : 0000.
STLC7549
34/35
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相關代理商/技術參數(shù)
參數(shù)描述
STLC7550 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW POWER LOW VOLTAGE ANALOG FRONT END
STLC7550TQF7 功能描述:電信線路管理 IC Lo-V Analg Front-End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
STLC7550TQF7TR 功能描述:電信線路管理 IC Lo-V Analg Front-End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
STLC7550TQFP 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW POWER LOW VOLTAGE ANALOG FRONT END
STLC75C53TQFP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MODEM
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