參數(shù)資料
型號： STLC7549
廠商： 意法半導(dǎo)體
元件分類： Codec
英文描述： Stereo Audio/MODEM/Telephony Codec(立體聲音頻/調(diào)制解調(diào)器/電話編解碼器)
中文描述： 立體聲音頻/調(diào)制解調(diào)器/語音編解碼器（立體聲音頻/調(diào)制解調(diào)器/電話編解碼器）
文件頁數(shù)： 24/35頁
文件大?。?/td> 335K
代理商： STLC7549
(N = 1, for MCLKA)
MCLKx
SCLKx
FSYNCx
SINx
SOUTx
D1
D0
D15
D14
D13
D12
D1
Bit63
D15
D14
D13
D12
Bit0
Bit1
D0
7
Figure 20 :
SerialInterfaceTiming
ALDIR
ALDOR
ARDOR
ARDIR
STAR
R0
GPOR
1
CLOCK
GENERATOR
ISR1
IBR1
16 bits
16 bits
FSYNC1
(RX1)
SCLK1
16 bits
FSYNC1
MCLKA
INDEX
REGISTER
SIN1
SCLK1
OSR1
FSYNC1
SOUT1
SCLK1
21
Registers
(RX1) (WX1)
OBR1
(WX1)
16 bits
Rx1, Wx1 internalsignals
7
Figure 21 :
Audio Serial InterfaceBlock Diagram
SERIALINTERFACE
SerialInterface Operation
Serial data input is initiated by a frame synchro
signal(FSYNC). The datais clockedfromSIN into
the input shift register (ISR) on the falling edge of
SCLK and transfered to the input buffer register
(IBR) when a complete 16-bit word has been re-
ceived, the register is loaded 8 bits clocks later.
Datais assumedto be received MSB first.
Serial data output is initiated by a frame synchro
signal(FSYNC).The16-bitdatawordisloadedinto
theoutputshift register(OSR)and serially clocked
out of OSRto SOUT on the rising edge of SCLK.
Thedata/indexregisterof SOUT1refertotheindex
registerset of SIN1 within the same frame.
The SCLK is 64 timesFSYNC. Thismean that the
frame contains four slots of 16 bits.The time slots
used for circuit function are indicated on the next
paragraph.
Serialport 1 and 2
- Frame SynchronizationOutput (FSYNC)
- Serial Bit Clock Output (SCLK)
- Input Serial Register(ISR)
- Input Buffer Register (IBR)
- Serial Input Data (SIN)
- Output BufferRegister
- Output Serial Register(OSR)
AudioSerial InterfaceOne
(Figures21 and 22)
- Audio Left Data Input Register (ALDIR)
- Audio Left Data Output Register (ALDOR)
- Audio Right Data Input Register(ARDIR)
- Audio Right Data Output Register(ARDOR)
- IndexRegister (R0 to R20)
- GeneralPurposeOutput Register (GPOR)
- StatusAudio Register
Modem and TelephoneSerial InterfaceTwo
(Figures 23 and 24)
- Modem Data InputRegister(MDIR)
- Modem Data Output Register (MDOR)
- TelephoneData Input Register (TDIR)
- TelephoneData Output Register(TDOR)
STLC7549
24/35
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參數(shù)描述
STLC7550 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW POWER LOW VOLTAGE ANALOG FRONT END
STLC7550TQF7 功能描述:電信線路管理 IC Lo-V Analg Front-End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
STLC7550TQF7TR 功能描述:電信線路管理 IC Lo-V Analg Front-End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
STLC7550TQFP 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW POWER LOW VOLTAGE ANALOG FRONT END
STLC75C53TQFP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MODEM
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