參數(shù)資料
型號： STA450A
廠商： 意法半導(dǎo)體
英文描述： XMRADIO SDARS SERVICE LAYER & SOURCE DECODER
中文描述： XMRADIO衛(wèi)星數(shù)字收音機(jī)服務(wù)層
文件頁數(shù)： 9/66頁
文件大?。?/td> 439K
代理商： STA450A
9/66
STA450A
N = pllsys_Nmodulo
M = pllsys_Mmodulo
The System PLL registers are configured through an indirection mechanism using the HOST_pll_add,
HOST_pll_data and HOST_pll_cmd registers; the HOST_pll_cmd register allows to update the control registers
of the PLL.
There are two levels of registers (Level 1 & Level 2). The first level of registers (Level 1) is configured through
the indirection mechanism. The second level of registers (Level 2) is a copy of the previous level in order to
update all the configuration bits at the same time. This mechanism avoids to have, during the configuration
phase, intermediate configurations that are not in line with the final desired configuration.
Assuming a 23.92MHz CLK input frequncy and CLK_M[1:0] = “11”, the default system frequency is 59.8MHz
See also the register description.
The Audio PLL
The "internal_pcmclk" of STA450A can be provided by two different sources: the Audio PLL or the OCLK port
of the chip.
The "m5" multiplexor and the direction of the OCLK tri-state port are configured by the register HOST_Pllpcm
(address 0x12).
An Audio PLL is embedded in STA450A.
The particularity of STA450A Audio PLL is the possibility to modify the Audio Sampling Frequency (LRCKT) in
steps of a few p.p.m. to compensate dynamically the audio sampling frequency offset between the receiver and
the broadcasting station; this compensation produces a jittering effect outside the audible range.
The STA450A receives from the STA400A (Channel Decoder) a dedicated signal every 432ms (PLL_SYNC)
and uses this signal to perform the audio sampling rate compensation; the control is done by the DSP core up-
dating the internal PLL registers.
Some PLL configuration registers are made available to the user to configure the PCM output according to the
used DAC.
The programmation for the desired Fs should be accomplished for both the Fs = 48KHz and Fs =
44.1KHz families before the start-up of the DSP (write in the register 0 x 4D)
The OCLK frequency can be derived from the following formula:
– X is the value of the HOST_APLL48_XDIV register (HOST_APLL441_XDIV) register.
– M is the value of the HOST_APLL48_MDIV register (HOST_APLL441_MDIV) register.
– N is the value of the HOST_APLL48_NDIV register (HOST_APLL441_NDIV) register.
– FRAC is the decimal value of the concatenated registers HOST_APLL48_LSB and
HOST_APLL48_MSB (HOST_APLL441_LSB and HOST_APLL441_MSB) as follows:
FRAC = 256 * HOST_APLL48_MSB + HOST_APLL48_LSB (= 256 * HOST_APLL441_MSB +
HOST_APLL441_LSB)
The changes in the registers are not effective once the DSP has been started.
OCLK_freq
+
1
X
-------------
1
+
N
----------------------------
M
1
-----------------
+
+
=
相關(guān)PDF資料
PDF描述
STA508 40V 4.5A QUAD POWER HALF BRIDGE
STABP01 GT 7C 7#16S SKT PLUG RTANG
STABP01D GT 5C 5#16S SKT PLUG
STB10NA40 N-Channel Enhancement Mode Fast Power MOS Transistor(N溝道增強(qiáng)模式快速功率MOSFET)
STB10NC50-1 CAP OXI NIOB 47UF 10V 20% SMD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
STA4527 制造商:Motorola Inc 功能描述:
STA457C 制造商:Sanken Electric Co Ltd 功能描述:Box
STA457C_06 制造商:SANKEN 制造商全稱:Sanken electric 功能描述:PNP + NPN Darlington H-bridge
STA458C 制造商:SANKEN 制造商全稱:Sanken electric 功能描述:PNP+NPN H-bridge
STA460C 制造商:Sanken Electric Co Ltd 功能描述:TRANSISTOR ARRAY W/DIO 制造商:ALLEGRO 功能描述:Array for Sink Drive with Built-in Avalanche Diode 制造商:Allegro MicroSystems LLC 功能描述:Array for Sink Drive with Built-in Avalanche Diode
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*