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參數(shù)資料
| 型號(hào)： | STA450A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | XMRADIO SDARS SERVICE LAYER & SOURCE DECODER |
| 中文描述： | XMRADIO衛(wèi)星數(shù)字收音機(jī)服務(wù)層 |
| 文件頁數(shù)： | 19/66頁 |
| 文件大?。?/td> | 439K |
| 代理商： | STA450A |
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19/66
STA450A
Hardware Reset
: 0
Description
Bit [1:0]
00: no action is performed on the configuration registers of the Level 1.
01: Read action of the configuration registers. During this phase, the content of a selected (by
HOST_pll_add) configuration register of the Level 1 is copied into the HOST_pll_data register.
10: Write action of the configuration registers. During this phase, the content of the
HOST_pll_data
register is copied into a selected (by HOST_pll_add) configuration register of the Level 1.
11: do not use.
The bit controls the transfer of the data between the Level 1 and the Level 2 for the System
PLL. When this bit is set, all the registers of the Level 1 (sys_ndiv, sys_pdiv, sys_setupH,
sys_setupL, sys_enable) are copied into the registers of the Level 2 at the same time.
When this bit is cleared, all the Level 2 registers have a stable state independently of the Level
1 registers.
Reserved
This bit must be used when switching from one System PLL configuration to the other one.
This bit must be used in conjunction with the bit [2].
Bit 2
Bit3
Bit 4
HOST_Plladd
Address
Type
Software Reset
Hardware Reset
: 0x1D
: R/W
: 0
: 0
Description
In the follow table the description of the registers addressable by the HOST_Plladd to control the system PLL
7
6
5
4
3
2
1
0
1D
Add
Name
Size
Mode
SW
Reset
HW
Reset
Comment
3
pllsys_disable
1
R - W
NC
0
System PLL disable control
0 : system PLL enabled
1 : system PLL disabled
4
pllsys_F_low
8
R - W
NC
0
8 low bits of Fractional value for
system PLL
5
pllsys_F_high
8
R - W
NC
0
8 high bits of Fractional value for
system PLL
6
pllsys_S
5
R - W
NC
2
S divider for system PLL
7
pllsys_N
4
R - W
NC
1
N divider for system PLL
8
pllsys_X
7
R - W
NC
0
X divider for system PLL
9
pllsys_M
5
R - W
NC
9
M divider for system PLL
10(0xA)
pllsys_update_frac
1
R - W
NC
0
Update Fractional value for
system PLL
12(0xC)
pllsys_paddiv
4
R - W
NC
3
pad clock divider
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