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參數(shù)資料
| 型號(hào)： | STA450A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | XMRADIO SDARS SERVICE LAYER & SOURCE DECODER |
| 中文描述： | XMRADIO衛(wèi)星數(shù)字收音機(jī)服務(wù)層 |
| 文件頁(yè)數(shù)： | 29/66頁(yè) |
| 文件大小： | 439K |
| 代理商： | STA450A |
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STA450A
HOST_DataPortBitRate
Address
Type
Software Reset
Hardware Reset
: 0x5F
: R/W
: NA
: NA
Description
Data port bit rate / 1K (for bitrates
≥
128Kbps 0xFF is reported)
10: Synchronised
HOST_EVENTINTE 4-5
Address
Type
Software Reset
Hardware Reset
: 0x66 - 0x67
: R - W
: NA
: NA
Description
These registers are associated to event condition inside the SDEC.
The SDEC contains a 16 bits interrupt register associated with 16 bits enable register.
A bit set in this register will enable the generation of an external interrupt on the interrupt line.
The interrupt associated with each bit is given in the register INT description.
HOST_EVENTINT 4-5
Address
Type
Software Reset
Hardware Reset
: 0x68 - 0x69
: R - W
: NA
: NA
Description
These registers are associated to event condition inside the SDEC.
A bit set in this table indicates the corresponding event has been occurred. Whenever the corresponding
bit in the INTE table has been set an external interrupt is generated.
To clear the bit a fast command has to be issued (see command description).
7
6
5
4
3
2
1
0
5F
7
6
5
4
3
2
1
0
66
67
INTE[15:8]
INTE[7:0]
7
6
5
4
3
2
1
0
68
69
INT[15:8]
INT[7:0]
Name
Reg
Bit
Comment
Fast extraction Loc0
0x68
0x01
Channel fast extraction for Loc0 successful
Fast extraction Loc1
0x02
Channel fast extraction for Loc1 successful
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