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參數(shù)資料
| 型號： | STA450A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | XMRADIO SDARS SERVICE LAYER & SOURCE DECODER |
| 中文描述： | XMRADIO衛(wèi)星數(shù)字收音機(jī)服務(wù)層 |
| 文件頁數(shù)： | 13/66頁 |
| 文件大?。?/td> | 439K |
| 代理商： | STA450A |
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STA450A
1.7 Test Interfaces (RS232)
The STA450A provides a RS232 RX and a RS232TX interfaces for testing purposes.
2.0 I2C BUS SPECIFICATION
The STA450A supports the I2C protocol to communicate with the System Controller; the STA450A is always a
slave in its communication to the System Controller.
2.1 COMMUNICATION PROTOCOL
A data change on the SDA line must only occur when SCLKI2C clock is low except for START and STOP con-
ditions. In that case, the transition is done when the clock is High.
A START condition is identified by a High to Low transition of the SDA line while the clock signal is High. A
START condition must precede any command for a data transfer.
A STOP condition is identified by a Low to High transition of the SDA line while the clock signal SCLKI2C is
High. A STOP condition terminates the communications between the IC and the master of the I2C bus.
An Acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either the master or the
slave, releases the SDA line after sending 8 bits of data. During the 9th clock pulse, the receiver pulls the SDA
line to Low to acknowledge the reception of 8 bits of data.
During the data transfer, the I2C slave interface of the IC samples the SDA line on the rising edge of the
SCLKI2C clock. The SDA signal has to be stable during the rising edge of the clock and the data can change
only when the SCLKI2C clock line is low.
2.2 DEVICE ADDRESSING
To start the communications between the master and the IC, the master must initiate the transfer with a START
condition. Then, the master has to send on the SDA line 8 bits (MSB first) corresponding to the device I2C ad-
dress (7 bits) and the mode bit RW (Read or Write).
The 7 most significant bits are the address of the device. For the STA450A the address is 0x5C (1011100 ad-
dress on 7 bits).
The 8th bit (LSB) selects a read (bit set to 1) or write (bit set to 0) operation. After a START condition, the IC
I2C slave interface identifies on the I2C bus the device address and, if the address matches, the IC acknowl-
edges this match on the SDA line during the 9th bit time frame. The byte following the device identification byte
is the address of the Host register to be accessed.
2.2.1
This mode is used for the initialization of the Host address register (sub-address value). The Host address reg-
ister is the register that points the data register to be accessed (read or write).
Sub-address initialization
2.2.2
The second mode, the multiple write, exploits the autoincrementation of the sub-address pointer to avoid to ini-
tialize, for sequential accesses of the Host registers, the sub-address at each write operation. The length of a
multiple write is limited to the size of the Host register area (256 locations).
After a writing in the I2C interface a interrupt is generated to the core if the System controller set the bit in the
HOST_Cmd0 register.
"Sub-address + single write" & "Sub-address + multiple write"
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