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參數資料
| 型號： | STA450A |
| 廠商： | 意法半導體 |
| 英文描述： | XMRADIO SDARS SERVICE LAYER & SOURCE DECODER |
| 中文描述： | XMRADIO衛(wèi)星數字收音機服務層 |
| 文件頁數： | 8/66頁 |
| 文件大?。?/td> | 439K |
| 代理商： | STA450A |
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STA450A
8/66
Figure 5. STA450A Clocks Generation System
The system clock
The system clock sent to the DSP core and the peripherals can be derived from 4 sources of clock and the se-
lection is performed by m4. The control of m4 is performed by the 2 input pins (CLK_M1 & CLK_M0):
– 00 sys_clk = CLK_IN
– 01 sys_clk = CLK_IN divided by 2
– 10 sys_clk = sys_clockout
– 11sys_clk = sys_clockout divided by 2
In the chip, the duty cycle of the internal system clock must be as close as possible 50%.
When the sys_clk is derived from the external clock source (
CLK_IN
), the divider by 2 can be used to ensure a
50% duty cycle.
When the sys_clk is derived from the system PLL, the duty cycle of the sys_clockout signal is 50%. The divider
by 2 can be used to slow down the clock at a lower frequency than the minimum that can achieve the System
PLL.
The CLK_OUT pad is driven by the sys_clk divided by a programmable division factor ranging from 1 to 16; the
sys_clk frequency is divided by 2 * (N+1), where N is the value programmed with register sys_paddiv [3:0].
Configuration Equations for the System PLL:
X = pllsys_Xmodulo
MMDSP +
CORE
PCM INTERFACE
USSIO0
sysclk
sysclk
sysclk
sysclk
USSIO1
USSIO2
USSIO3
internal_pcmclk
MMIO
PERIPHERALS
DIV
MD+1
PFD
FREF
FIN
PLL DISABLE
/ 2
/ 2
C3
R
C
VCO
DIV
MD+1
DIV
MD+1
SWITCHING
CIRCUIT
CHARGE
PUMP
SYSTEM PLL
sys_paddiv(3:0)
sys_clockout
/ 2
(N+1)
OCLK
CLK_IN
CLKOUT
Emulation Unit
RS232 Interfaces
Host Interface
Timers Ext Interrupt
GPIO
I2C master
IO ROM
IT remap
FRAC0
m4
sys_clk
m5
DIV
MD+1
PFD
FREF
FIN
PLL DISABLE
C3
R
C
VCO
DIV
MD+1
DIV
MD+1
audio sample counter
SWITCHING
CIRCUIT
CHARGE
PUMP
AUDIO PLL
audio_clockout
external filter
FRAC0
D02AU1415
F
out
+
X
1
-------------
Fref
IN
N
+
1
----------------
M
1
65536
----------------------------
+
+
=
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