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STA450A
HOST_ERRINTEH - HOST_ERRINTEL
Address
Type
Software Reset
Hardware Reset
: 0x4A - 0x49
: R/W
: NA
: NA
Description
These registers are associated to error condition inside the STA450A.
The STA450A contains a 16 bit interrupt register associated with 16 bit enable register.
A bit set in this register will enable the generation of an external interrupt on the interrupt line. The
interrupt associated with each bit is given in the register INT description.
HOST_ERRINTH - HOST_ERRINTL
Address
Type
Software Reset
Hardware Reset
Description
These registers are associated to error condition inside the STA450A.
A bit set in this table indicates the corresponding event has been occurred. Whenever the corresponding
bit in the INTE table has been set an external interrupt is generated.
To clear the bit a fast command has to be issued (see command description).
: 0x4B - 0x4C
: R/W
: NA
: NA
7
6
5
4
3
2
1
0
4A
INTE[15:8]
49
INTE[7:0]
7
6
5
4
3
2
1
0
4C
INT[15:8]
4B
INT[7;0]
Name
Reg
Bit
Comment
Service Layer Lost
Synchronization
0x4B 0x01 Service Layer Lost synchronisation due to communication error with
CDEC
TSCC RSError
0x02 TSCC have RS errors
Bitstream Communication Failure
0x04 The format of communication is not compatible with the bitstream
input I/F. The DSP need to be restarted
Service Layer incorrect status
0x08 Service Layer have reached an incorrect status.
NoBacFromCdec
0x10 The BAC wasn’t received from the CDEC in the last frame
Rollback
0x20 Error from decryption
PicIOError
0x40 Communication error with the CAP device
Audio Decoder Not Working
0x80 Error in the audio decoder
NV Memory Unreadable
0x4C 0x01 Data corrupted in the NVM
ExtractionError_0
0x02 Some error occurs during extraction of channel in location 0, to obtain
detailed situation System Controller must raise a command. At the
time of this command is raised the DSP clear the error buffer
ExtractionError_1
0x04 Some error occurs during extraction of channel in location 1, to obtain
detailed situation System Controller must raise a command. At the
time of this command is raised the DSP clear the error buffer