參數(shù)資料
型號(hào)： ST52E430B/D
廠商： STMICROELECTRONICS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 20 MHz, MICROCONTROLLER, CDIP32
封裝： WINDOWED, SHRINK, CERAMIC, DIP-32
文件頁(yè)數(shù)： 68/120頁(yè)
文件大小： 502K
代理商： ST52E430B/D
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ST52T430/E430
The 16-bit Prescaler x divides the master clock,
CLKM, or, only for TIMER0, the external T0CLK
signal, by the 16-bit Prescaler x.
NOTE: The external clock signal, applied on
T0CLK pin, must have a frequency at least two
times smaller than the internal master clock.
The Prescaler x output can be selected by setting
PRESCx bit of REG_CONF6, REG_CONF9 and
REG_CONF11 registers (see tables 9.2, 9.5 and
9.7).
When the Counter x reaches the Peripheral
Register PWM_x_COUNT value (Compare Value),
the TIMERxOUT signal changes from high to low
level, up to the next counter start.
The period of the PWM signal is obtained by using
the following relation:
T
PWM x RELOAD
TMRCLKx
=-
(_ _
)
255
where TMRCLKx is the output of the 16-bit
prescaler x.
The duty cycle of the PWM signal is controlled by
the Output Register PWM_x_COUNT:
Ton =(PWM_x_COUNT- PWM_x_RELOAD)*
TMRCLKx
If the Output Register PWM_x_COUNT value is 255
the TIMERxOUT signal is always at high level.
If the Output Register PWM_x_COUNT is 0, or less
than the PWM_x_RELOAD value, TIMERxOUT
signal is always at low level.
NOTE. If PWM_x_RELOAD value increases the
duty cycle resolution decreases.
By using a 20 MHz clock master it is possible to
obtain a PWM frequency in the range 1.2 Hz to
78.43 Khz.
NOTE: The Timer, before to use a new values of
the counter, has to complete the previous
counting phase. If the counter value is changed
during a counting, the new value of the timer
counter is used only at the end of the previous
counting phase. This happens both in timer
and in PWM mode.
9.3 Timer Interrupt
The TIMERx can be programmed to generate an
Interrupt request until the end of the count or when
there is an external TSTART signal. The Timer can
generate programmable Interrupts in to 4 different
modes:
Interrupt mode 1: Interrupt on counter Stop.
Interrupt mode 2: Interrupt on Rising Edge of
TIMEROUT.
Interrupt mode 3: Interrupt on Falling Edge of
TIMEROUT.
Interrupt mode 4: Interrupt on both edges of
TIMEROUT.
The Interrupt mode can be selected by means of
INTSLx and INTEx bits of the REG_CONF5,
REG_CONF8 and REG_CONF10 registers (see
tables 9.1, 9.4 and 9.6).
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