參數(shù)資料
型號(hào): ST52E430B/D
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, UVPROM, 20 MHz, MICROCONTROLLER, CDIP32
封裝: WINDOWED, SHRINK, CERAMIC, DIP-32
文件頁(yè)數(shù): 51/120頁(yè)
文件大?。?/td> 502K
代理商: ST52E430B/D
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ST52T430/E430
5.3.2 Halt Mode
The Halt mode is the MCU lowest power
consumption mode. The Halt mode is entered by
executing the HALT instruction. The internal
oscillator is turned off, causing all internal
processing to be stopped, including the
operations of the on-chip peripherals. The Halt
mode cannot be used when the watchdog is
enabled. If the HALT instruction is executed while
the watchdog system is enabled, it will be skipped
without modifying the normal CPU operations.
In Halt mode the external interrupt is enabled. If an
interrupt occurs, the CPU becomes active.
The MCU can exit the Halt mode upon reception of
an external interrupt or a reset. The oscillator is
then turned on and a stabilization time is provided
before restarting the CPU operations. The
stabilization time is 4096 CPU clock cycles. After
the start up delay, the CPU restarts the operations.
Wake-Up from HALT
The device can wake up from HALT through one of
the following events:
1) External interrupt
2) External reset by fetching the reset vector
Wake-up is regardless of the state of the
External Interrupt mask. When the external
interrupt is disabled, the device after the start up
delay continues execution at the instruction after
the HALT instruction. When the External interrupt is
enabled, the device after the start up delay
continues executing the External Interrupt service
routine.
OSCILLATOR
PERIPHERALS CLOCK
CPU CLOCK
EXT. INTERRUPTS
OFF
ENAB.
HALT INSTRUCTION
WATCHDOG
ENABLED
HALT INSTRUCTION
SKIPPED
YES
RESET
EXTERNAL
INTERRUPT
EXT. INTERRUPTS
PERIPHERALS CLOCK
CPU CLOCK
OSCILLATOR
ON
DIS.
ON
YES
NO
YES
NO
4096 CPU CLOCK
CYCLES DELAY
SERVICE INTERRUPT or
RESTART THE USER PROGRAM
Figure 5.5 HALT Flow Chart
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