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| 型號(hào)： | ST52E430B/D |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, UVPROM, 20 MHz, MICROCONTROLLER, CDIP32 |
| 封裝： | WINDOWED, SHRINK, CERAMIC, DIP-32 |
| 文件頁(yè)數(shù)： | 42/120頁(yè) |
| 文件大?。?/td> | 502K |
| 代理商： | ST52E430B/D |
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ST52T430/E430
INT_ADC
INT_TIMER/PWM2
INT_SCI
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
INTERRUPT
VECTORS
INT_EXT
18
19
20
INT_TIMER/PWM1
INT_TIMER/PWM0
Figure 4.2. Interrupt Vectors Mapping
4 INTERRUPTS
The Control Unit (CU) responds to peripheral
events and external events through its interrupt
channels.
When such an event occurs, if the related interrupt
is not masked and according to a priority order, the
current program execution can be suspended to
allow the CU to execute a specific response
routine.
Each interrupt is associated with an interrupt
vector that contains the memory address of the
related interrupt service routine. Each vector is
located in the Program Space (EPROM Memory)
at a fixed address (see Interrupt Vectors table fig.
4.2).
4.1 Interrupt Functionment
If, at the end of an arithmetic or logic instruction,
there are pending interrupts, the one with the
highest priority is passed. To pass an interrupt
means to store the arithmetic flags and the current
PC in the stack and execute the associated
Interrupt routine, whose address is located in two
bytes of the EPROM memory location between
address 3 and 20.
The Interrupt routine is performed as a normal
code checking, at the end of each instruction, if an
higher priority interrupt has to be passed. An
Interrupt request with the higher priority stops the
lower priority Interrupt. The Program Counter and
the arithmetic flags are stored in the stack.
With the instruction RETI (Return from Interrupt)
the arithmetic flags and Program Counter (PC) are
restored from the top of the stack. This stack was
already described in the section 2.2.1.
An Interrupt request cannot stop the processing of
the fuzzy rules, but this is passed only after the end
of a fuzzy rule or at the end of a logic, or arithmetic,
instruction.
4.2 Global Interrupt Request Enabling
When an Interrupt occurs, it generates a Global
Interrupt Pending (GIP), that can be hanged up by
software. After a GIP a Global Interrupt Request
(GIR) will be generated and Interrupt Service
Routine associated to the interrupt with higher
priority will start.
In order to avoid possible conflicts between
interrupt masking set in the main program, or
inside macros, the GIP is hanged up through the
User Global Interrupt Mask or the Macro Global
Interrupt Mask (see fig.4.3).
UEGI/UDGI instruction switches on/off the User
Global Interrupt Mask enabling/disabling the GIR
for the main program.
NORMAL
PROGRAM
FLOW
INTERRUPT
SERVICE
ROUTINE
RETI
INSTRUCTION
INTERRUPT
Figure 4.1. Interrupt Flow
Global Interrupt
Pending
User Global
Interrupt Mask
Macro Global
Interrupt Mask
Global Interrupt
Request
Figure 4.3 Global Interrupt Request generation
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相關(guān)代理商/技術(shù)參數(shù) |
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| ST52E430K1B6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT INTELLIGENT CONTROLLER UNIT ICU Three Timer/PWMs, ADC, SCI |
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