參數(shù)資料
型號(hào)： ST52E430B/D
廠商： STMICROELECTRONICS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 20 MHz, MICROCONTROLLER, CDIP32
封裝： WINDOWED, SHRINK, CERAMIC, DIP-32
文件頁(yè)數(shù)： 60/120頁(yè)
文件大?。?/td> 502K
代理商： ST52E430B/D
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ST52T430/E430
If input voltage is greater than or equal to Vdda
(Voltage Reference high) then result is equal to
FFh (full scale) without overflow indication.
If input voltage is less than Vss (voltage reference
low) then the result is equal to 00h.
The A/D converter is linear and the digital result of
the conversion is given by the formula:
Digital result
xInput Voltage
referenceVoltage
=
255
Where Reference Voltage is Vdda -Vss.
The accuracy of the conversion is described in the
Electrical Characteristics Section.
The A/D converter is not affected by the WAIT
mode.
When the MCU enters HALT mode with A/D
converter enabled, the converter is disabled until
the HALT mode is exited and the start-up delay has
elapsed. A stabilization time is also required before
accurate conversions can be performed.
D7
D0
CH2 CH1 CH0 SCK SEQPOW LP STR
REG_CONF 3
START/STOP
CONVERSION MODE SEL
ON/OFF A/D
CONVERSION MODE SEL
CLOCK SELECTOR
CHANNELS SEL.
Figure 7.2. A/D Configuration Register (REG_CONF 3)
7.2.1 Operating Modes
Four main operating modes can be selected by
setting the values of the LP and SEQ bit in the A/D
configuration Register.
One Channel Single Mode
In this mode (SEQ = ‘0’’, LP = ‘0’) the A/D
provides an EOC signal after the end of channel
i-th conversion; then the A/D waits for a new start
event. The channel i-th is identified by the bit CH0,
CH1, CH2.
i.e CH(2:0) = ‘011’ means conversion of channel 3
then stop.
Multiple Channels Single Mode
In this mode (SEQ = ‘1’, LP = ‘0’) the A/D
provides an EOC signal after the end of the
channels sequence conversion identified by the
bit CH0, CH1, CH2 ; then the A/D waits for a new
start event.
i.e. CH(2:0) = ‘011’ means conversion of channels
0,1,2 and 3 then stop.
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