參數(shù)資料
型號(hào)： ST52E430B/D
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 20 MHz, MICROCONTROLLER, CDIP32
封裝： WINDOWED, SHRINK, CERAMIC, DIP-32
文件頁(yè)數(shù)： 47/120頁(yè)
文件大?。?/td> 502K
代理商： ST52E430B/D
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ST52T430/E430
4.5 Interrupt Priority
Seven priority levels are available: level 6 has the
lowest priority, level 0 has the highest priority.
Level 6 is associated to the Main Program, levels 5
to 1 are programmable by means of the priority
registers called REG_CONF17 and REG_CONF18
(see fig.4.5 and table 4.3); whereas the higher level
is related to the external interrupt (INT_EXT).
PWM/Timers, UART and ADC are identified by a
three-bits Peripheral Code (see Table 4.2); in order
to set the i-th priority level the user must write the
peripheral label i in the related INTi priority level.
i.e.
LDRC
10,
193
//(load
the
value
193=’11000001’ in the RAM Register 10)
LDRC
11,
168
//(load
the
value
168=’10101000’ in the RAM Register 11)
LDCR 17, 10
// set
the REG_CONF17=
‘11000001’
LDCR 18, 11
// set
the REG_CONF18=
‘10101000’
thus defining the following priority levels:
Bit
Name
Value
Level
0, 1,2
INT1
Peripheral
Code
High
3, 4,5
INT2
Peripheral
Code
Medium-High
6,7,8
INT3
Peripheral
Code
Medium-Low
9,10,11 INT4
Peripheral
Code
Low
12,13,14 INT5
Peripheral
Code
Very Low
Table 4.3. Conf. Register 17&18 Description
MAIN PROGRAM
5
4
3
2
1
0
INT2
INT0
INT2
INT1
INT2
INT3
INT4
MAIN PROGRAM
PRIORITY
LEVEL
INT2
INT0
INT4
INT1
INT3
6
Figure 4.6. Example of a Sequence of Interrupt Requests
n
Level 1: INT_PWM/TIMER0 (PWM/TIMER 0
Code: 001)
n
Level 2: INT_ADC (ADC Code: 000)
n
Level 3:INT_PWM/TIMER2 (PWM/TIMER 2
Code: 011)
n
Level 4: INT_UART (UART Code: 100)
n
Level 5: INT_PWM/TIMER1 (PWM/TIMER 1
Code: 010)
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