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參數(shù)資料
| 型號： | ST52E430B/D |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, UVPROM, 20 MHz, MICROCONTROLLER, CDIP32 |
| 封裝： | WINDOWED, SHRINK, CERAMIC, DIP-32 |
| 文件頁數(shù)： | 59/120頁 |
| 文件大?。?/td> | 502K |
| 代理商： | ST52E430B/D |
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ST52T430/E430
7. A/D CONVERTER
7.1 Introduction
The A/D Converter of ST52x430 is an 8-bit analog
to digital converter with up to 8 analog inputs
offering 8 bit resolution with a total accuracy of 1
LSB and a typical conversion time of 8.2 ms with a
20 MHz clock. This period also includes the 5.1 ms
of the integral Sample and Hold circuitry, which
minimizes the need for external components and
allows quick sampling of the signal for the
minimum warping effect and Integral conversion
error.
A conversion is performed in 82 A/D clock
pulses.
The A/D clock is derived from the clock master.
The maximum A/D clock frequency has to be 10
MHz, for this reason when the master clock is
higher than 10 MHz it has to be divided by 2 using
the bit SCK of the A/D configuration register
REG_CONF 3 (See table 7.1).
The A/D peripheral converts the input voltage with
a process of successive approximations using a
fixed clock frequency derived from the oscillator.
The conversion range is between the analog
Vss and Vdd references.
The converter uses a fully differential analog input
configuration for the best noise immunity and
precision performances, along with one separate
supply (Vdda), allowing the best supply noise
rejection.
Up to 8 multiplexed Analog Inputs are available. A
group of signals can be converted sequentially by
simply programming the starting address of the
last analog channel to be converted.
Single or continuous conversion mode are
available.
The result of the conversion is stored in an 8-bit
Input Registers (from IR 1 to IR 8).
The A/D converter is controlled through the
Configuration Register REG_CONF 3.
A Power-Down programmable bit allows to set the
A/D converter to a minimum consumption idle
status.
The ST52x430 Interrupt Unit provides one
maskable channel for the End of Conversion
(EOC)
7.2 Functional Description
The conversion is monotonic meaning the result
never decreases if the analog input does not and
never increases if the analog input does not.
PB0/AIN0
PB1/AIN1
PB2/AIN2
PB3/AIN3
PB7/PA7/AIN7
PB6/AIN6
PB5/AIN5
PB4/AIN4
ANALOG
MUX
SUCCESSIVE APPROXMATION
A/D CONVERTER
A/D CHANNEL 7
A/D CHANNEL 6
A/D CHANNEL 5
A/D CHANNEL 4
A/D CHANNEL 3
A/D CHANNEL 2
A/D CHANNEL 1
A/D CHANNEL 0
INPUT REGISTER
1 8
SAMPLE
HOLD
&
CH2
CH1
CH0
SCK
SEQ
POW
LP
STR
CONFIGURATION REGISTER 3
CONTROL
LOGIC
Figure 7.1. A/D Converter Structure
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