參數(shù)資料
型號: ST52E430B/D
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, UVPROM, 20 MHz, MICROCONTROLLER, CDIP32
封裝: WINDOWED, SHRINK, CERAMIC, DIP-32
文件頁數(shù): 43/120頁
文件大?。?/td> 502K
代理商: ST52E430B/D
29/120
ST52T430/E430
MEGI/MDGI instructions switches on/off the Macro
Global Interrupt Mask in order to ensure that the
macro will not be broken.
4.3 Interrupt Sources
ST52x430 manages interrupt signals generated by
the internal peripherals (PWM/Timers, UART and
Analog to Digital Converter) or coming from the
INT/PC0 pin. The External Interrupt can be
programmed to be active on the rising or falling
edge of INT/PC0 signal by setting the PEXTINT bit
of the Configuration Register 0.
Each peripheral can be programmed in order to
generate the associated interrupt; further details
are described in the related chapter.
4.4 Interrupt Maskability
The interrupts can be masked by configuring the
REG_CONF 0 by mean of LDCR, or LDCE,
instruction. The interrupt is enabled when the bit
associated to the mask interrupt is “1". Viceversa,
when the bit is ”0", the interrupt is masked and it is
kept pendent.
For example:
LDRC 10,6 //load the constant 6 in the
RAM Register 10
LDCR 0, 10 // set the CONF_REG 0 with
the value stored in the RAM Register 10
the result is CONF_REG0 =00000110 thus
enabling the interrupts coming from the ADC
(INT_ADC) and from the PWM/TIMER 0
(INT_PWM/TIMER0).
Bit
Name
Value
Description
0
MSKE
0
External Interrupt
Masked
1
External Interrupt
Not Masked
1
MSKAD
0
A/D Converter Interrupt
Masked
1
A/D Converter Interrupt
Not Masked
2
MSKTM0
0
PWM/TIMER 0Interrupt
Masked
1
PWM/TIMER 0 Interrupt
Not Masked
3
MSKTM1
0
PWM/TIMER 1 Interrupt
Masked
1
PWM/TIMER 1 Interrupt
Not Masked
4
MSKTM2
0
PWM/TIMER 2 Interrupt
Masked
1
PWM/TIMER 2 Interrupt
Not Masked
5
MSCI
0
SCI Interrupt Not Masked
1
SCI Interrupt Masked
6
PEXTINT
0
External Interrupt Polarity
Active on Rising Edge
1
External Interrupt Polarity
Active on Falling Edge
7
Not used
Reset Configuration ‘000000’
Table 4.1. Configuration Register 0
Description
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